mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 57

• Manufacturer Part Number: mc9s12uf32
• Description: System Chip Guide V01.05
• Manufacturer: Freescale Semiconductor, Inc

System on a Chip Guide — 9S12UF32DGV1/D V01.05
2.4 Detailed Signal Descriptions for 100-pin package
2.4.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.4.2 RESET — External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
the COP watchdog circuit. External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK
cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the RESET pin
low and a clocked reset sequence controls when the MCU can begin normal processing The RESET pin
includes an internal pull up device.
2.4.3 TEST — Test Pin
The TEST pin is reserved for test and must be tied to VSS in all applications.
2.4.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator. This pin should be connected to
VDDR in normal application of the device.
2.4.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched
to the MODC bit at the rising edge of RESET. In MCU expanded modes of operation, when instruction
tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction
word being read into the instruction queue. This pin always has an internal pull up.
2.4.6 RPU — USB D+ pull up resistor termination
RPU is an analog input for the USB physical layer module. Refer to USB20D6E2F block guide for further
information.
2.4.7 RREF — External bias resistor
RREF is an analog input for the USB physical layer module. Refer to USB20D6E2F block guide for
further information.
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