cop87l88rb National Semiconductor Corporation, cop87l88rb Datasheet
cop87l88rb
Related parts for cop87l88rb
cop87l88rb Summary of contents
Page 1
... COP8 software and hardware de- velopment tools. Device Memory (bytes) COP87L88EB 16k OTP EPROM COP87L89EB 16k OTP EPROM COP87L88RB 32k OTP EPROM COP87L89RB 32k OTP EPROM Key Features n CAN 2.0B (passive) bus interface, with Software Power save mode n 8-bit A/D Converter with 8 channels ...
Page 2
Basic Functional Description n CAN I/F — CAN serial bus interface block as described in the CAN specification part 2.0B (Passive) — Interface rates up to 250k bit/s are supported utilizing standard message identifiers n Programmable double buffered USART n ...
Page 3
... Connection Diagrams Order Number COP87L88EBV-XE or COP87L88RBV-XE Note: -X Crystal Oscillator -E Halt Mode Enabled Order Number COP87L89EBV-XE or COP87L89RBV-XE Plastic Chip Carrier Top View See NS Plastic Chip Package Number V44A Plastic Leaded Chip Carrier Top View See NS Plastic Chip Package Number V68A FIGURE 2. Connection Diagrams ...
Page 4
Connection Diagrams Pinouts for 44-Pin and 68-Pin Packages Port Type ALT Pin Function G0 I/O INT G1 I/O WDOUT G2 I/O T1B G3 I/O T1A CKO ...
Page 5
Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin DC Electrical Characteristics −40˚C T +85˚C A Parameter Operating Voltage ...
Page 6
DC Electrical Characteristics Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at V Note 4: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test ...
Page 7
CAN Comparator DC and AC Characteristics 4.8V V 5.2V, −40˚C T +85˚ Parameter Differential Input Voltage Input Offset Voltage Input Common Mode Voltage Range Input Hysteresis A/D Converter Specifications (4.5V V 5.5V) (V − 0.050V Parameter ...
Page 8
Typical Performance Characteristics www.national.com (−55˚ +125˚C) A DS100044-57 DS100044-59 DS100044-61 8 DS100044-58 DS100044-60 ...
Page 9
Pin Description V and GND are the power supply pins. CC CKI is the clock input. The clock can come from a crystal os- cillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See ...
Page 10
Pin Description (Continued) M4 Multi-input Wakeup or T2A M3 Multi-input Wakeup Multi-input Wakeup or SCK M1 Multi-input Wakeup or MOSI M0 Multi-input Wakeup or MISO Ports and N are general-purpose, bidirectional I/O ports. Any ...
Page 11
Functional Description with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers. The device has 192 bytes of RAM. Sixteen bytes of RAM ...
Page 12
Oscillator Circuits The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7. The CKI input frequency is divided by 10 ...
Page 13
Timers The device contains a very versatile set of timers (T0, T1 and T2). All timers and associated autoreload/capture registers power up containing random data. TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low ...
Page 14
Timers (Continued) dent of the microcontroller. The user software services the timer block only when the PWM parameters require updat- ing. In this mode the timer Tx counts down at a fixed rate of t Upon every underflow the timer ...
Page 15
Timers (Continued) TIMER CONTROL FLAGS The control bits and their functions are summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent PWM and ...
Page 16
Power Save Modes The device offer the user two power save modes of opera- tion: HALT and IDLE. In the HALT mode, all microcontrol- ler activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are ...
Page 17
Multi-Input Wakeup (Continued) nation of Port L bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the Reg: WKEN. The Reg: WKEN is an 8-bit read/write register, which con- tains a control ...
Page 18
Multi-Input Wakeup (Continued) The GIE (global interrupt enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global ...
Page 19
Multi-Input Wakeup (Continued) ceive wakeup condition. The CAN block has it’s own, dedi- cated receiver interrupt upon receive buffer full (see CAN Section). CAN Wake-Up: The CAN interface can be programmed to wake the device from HALT/IDLE mode. This is ...
Page 20
CAN Interface Block (Continued) Functional Block Description of the CAN Interface Interface Management Logic (IML) The IML executes the CPU’s transmission and reception commands and controls the data transfer between CPU, Rx/Tx and CAN registers. It provides the CAN Interface ...
Page 21
Functional Block Description of the CAN Interface (Continued) Receive/Transmit (Rx/Tx) Registers The Rx/Tx registers are 8-bit shift registers controlled by the TCL and the BSP. They are loaded or read by the Interface Management Logic, which holds the data to ...
Page 22
Functional Block Description of the CAN Interface (Continued) Output Drivers/Input Comparators The output drivers/input comparators are the physical inter- face to the bus. Control bits are provided to TRI-STATE the output drivers. A dominant bit on the bus is represented ...
Page 23
Functional Block Description of the CAN Interface (Continued) The PS2..PS0 bits fix the number of Prescaler clock cycles per bit time for phase segment 1 and phase segment 2. The PS2..PS0 bits also set the synchronization Jump Width to a ...
Page 24
Functional Block Description of the CAN Interface (Continued) erate an interrupt by setting the Can Error Interrupt Enable bit (CEIE). This bit has to be cleared by the user’s software. CEIE CAN Error Interrupt Enable If set by the user’s ...
Page 25
Functional Block Description of the CAN Interface (Continued) cally reset through a read of the Receive/Transmit Status register the responsibility of the user to clear this bit by reading the receive/transmit status register (RTSTAT), be- fore the next ...
Page 26
Basic CAN Concepts MULTI-MASTER PRIORITY BASED BUS ACCESS The CAN protocol is message based protocol that allows a 11 total of 2032 (= 2 −16) different messages in the standard 29 format and 512 million (= 2 −16) different messages ...
Page 27
Frame Formats INTRODUCTION There are basically two different types of frames used in the CAN protocol. The data transmission frames are: data/remote frame The control frames are: error/overload frame Note: This device cannot send an overload frame as a result ...
Page 28
Frame Formats (Continued) A remote frame is identical to a data frame, except that the RTR bit is “recessive”, and there is no data field. IDE = Identifier Extension Bit The IDE bit in the standard format is transmitted “dominant”, ...
Page 29
Frame Formats (Continued) ACK FIELD The ACK field is two bits long and contains the ACK slot and the ACK delimiter. The ACK slot is filled with a “recessive” bit by the transmitter. This bit is overwritten with a “dominant” ...
Page 30
Frame Formats (Continued) FIGURE 23. Interframe Space for Nodes Which Are Error Passive module 1 = error active transmitter detects bit error at t2 module 2 = error active receiver with a local fault at t1 module 3 = error ...
Page 31
Frame Formats (Continued) module 1 = error active receiver with a local fault at t1 module 2 = error passive transmitter detects bit error at t2 module 3 = error passive receiver detects stuff error at t2 FIGURE 25. Error ...
Page 32
Frame Formats (Continued) ERROR MANAGEMENT AND DETECTION There are multiple mechanisms in the CAN protocol, to de- tect errors and to inhibit erroneous modules from disabling all bus activities. FIGURE 26. Order of Bit Transmission within a CAN Frame The ...
Page 33
Frame Formats (Continued) The counters are modified by the device’s hardware accord- ing to the following rules: TABLE 8. Receive Error Counter Handling Condition A receiver detects a Bit Error during sending an active error flag. A receiver detects a ...
Page 34
Frame Formats (Continued) A) Synchronization segment B) Propagation segment www.national.com FIGURE 28. Bit Timing FIGURE 29. Resynchronization 1 FIGURE 30. Resynchronization 2 34 DS100044-33 DS100044-34 DS100044-35 ...
Page 35
Interrupts INTRODUCTION Each device supports fourteen vectored interrupts. Interrupt sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. ...
Page 36
Interrupts (Continued) MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of ...
Page 37
Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in- terrupt occurs and the VIS instruction ...
Page 38
Interrupts (Continued) VIS Execution When the VIS instruction is executed it activates the arbitra- tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest ...
Page 39
Interrupts (Continued) FIGURE 33. VIS Flowchart 39 DS100044-56 www.national.com ...
Page 40
Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . INT_EXIT: ...
Page 41
Interrupts (Continued) NON-MASKABLE INTERRUPT Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag is reset to ...
Page 42
Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of underfined ROM gets zeros. The opcode for soft- ware interrupt is zero. If the ...
Page 43
MICROWIRE/PLUS (Continued) MICROWIRE/PLUS Master Mode Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to enable ...
Page 44
Serial Peripheral Interface The Serial Peripheral Interface (SPI) is used in master-slave bus systems synchronous bidirectional serial commu- nication interface with two data lines MISO and MOSI (Mas- ter In Slave Out, Master Out Slave In). A ...
Page 45
Serial Peripheral Interface The SPIU Control Register Bit 7 Bit 6 SRIE STIE SRIE SPI Receive Interrupt Enable 0 — disable receive interrupt 0 — enable receive interrupt B6 STIE SPI Transmit buffer Interrupt Enable 0 — ...
Page 46
Serial Peripheral Interface B[4:3] SPIMOD[1:0] SPI operation mode select SPIMOD[1: Slave mode, — SCK is SPI clock input — MISO is SPI data output — MOSI is SPI data input — slave select input 1 0: ...
Page 47
Serial Peripheral Interface SESSEN = 1, SCE = 0. If MOSI = 0 at the falling edge of SS, the ESS programming mode is detected and all N-port alternate functions are enabled. (Continued) FIGURE 39. Programming the SPI Expander FIGURE ...
Page 48
SPI Status Register a) Slave mode; rising SCK edge is active edge. (SPIMOD[1,0] = [0,0], SCE = 0) b) Slave mode; falling SCK edge is active edge. (SPIMOD[1,0] = [0,0], SCE = 1) a) Master mode; rising SCK edge is ...
Page 49
SPI Status Register (Continued) Bit 7 Bit 6 SRORN SRBNE 0 0 The SPI Status Register is a read only register. B7 SRORN SPI receiver overrun. This bit is set on the attempt to overwrite valid data in the RX ...
Page 50
SPI Status Register SPI SYNCHRONIZATION After the SPI is enabled (SPIEN = 1), the SPI internal re- ceive and transmit shift clock is kept disabled until SS be- comes inactive. This includes SS being active at the time SPIEN is ...
Page 51
A/D Converter (Continued) OPERATING MODES The A/D converter supports ratiometric measurements. It supports both Single Ended and Differential modes of opera- tion. Four specific analog channel selection modes are sup- ported. These are as follows: Allow any specific channel to ...
Page 52
A/D Converter (Continued) on for seven clock cycles. If the A single conversion mode, the conversion complete signal from the A/D will gen- erate a power down for the A/D converter and will clear the ADBSY bit in ...
Page 53
USART The device contains a full-duplex software programmable USART. The USART Figure 44 consists of a transmit shift register, a receiver shift register and seven addressable reg- isters, as follows: a transmit buffer register (TBUF), a re- ceiver buffer register ...
Page 54
USART (Continued) USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. DESCRIPTION OF USART REGISTER BITS ENU-USART Control and Status Register (Address at 0BA) PEN PSEL1 XBIT9/ CHL1 CHL0 PSEL0 ...
Page 55
USART (Continued) ERI = 0 Interrupt from the receiver is disabled. ERI = 1 Interrupt from the receiver is enabled. ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset. ETI = 0 Interrupt from the transmitter ...
Page 56
USART Operation (Continued) Note that the XBIT9/PSEL0 bit located in the ENU register serves two mutually exclusive functions. This bit programs the ninth bit for transmission when the USART is operating with nine data bits per frame. There is no ...
Page 57
Baud Clock Generation write registers shown in Figure 47 . Note that the 11-bit Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset. As shown in Table Prescaler Factor of ...
Page 58
Baud Clock Generation TABLE 16. Baud Rate Divisors (1.8432 MHz Prescaler Output) Baud Rate Divisor −1 (N-1) 110 (110.03) 134.5 (134.58) 150 300 600 1200 1800 2400 3600 4800 7200 9600 19200 38400 Note: The entries in Table 16 assume ...
Page 59
Attention Mode (Continued) automatically at this point, so that data characters as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding either to ac- cept the subsequent data stream (by leaving the ...
Page 60
WATCHDOG Operation WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the COP888 WATCH- DOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and Clock Monitor detector cir- cuits are inhibited during RESET. • Following RESET, the ...
Page 61
Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads as All Ones) 0080 ...
Page 62
Memory Map (Continued) Address 00CB A/D Converter Control Register (Reg:ENAD) 00CC A/D Converter Result Register (Reg:ADRSLT) 00CD to Reserved 00CE 00CF IDLE Timer Control Register (Reg:ITMR) 00D0 PORTLD, Port L Data Register 00D1 PORTLC, Port L Configuration Register 00D2 PORTLP, ...
Page 63
Addressing Modes (Continued) Absolute The mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any loca- tion in the ...
Page 64
Instruction Set (Continued) INSTRUCTION SET ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical EXclusive OR IFEQ ...
Page 65
Instruction Set (Continued) INSTRUCTION SET (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration [SP] PL, [SP−1] ...
Page 66
Instruction Set (Continued) INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be skipped, where ...
Page 67
Nibble Lower 67 www.national.com ...
Page 68
Development Tools Support OVERVIEW National is engaged with an international community of inde- pendent 3rd party vendors who provide hardware and soft- ware development tool support. Through National’s interac- tion and guidance, these tools cooperate to form a choice of ...
Page 69
Development Tools Support (Continued) COP8 Real-Time Emulation Tools • COP8-DM: MetaLink Debug Module. A moderately priced real-time in-circuit emulation tool, with COP8 de- vice programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emula- tion cables and adapters. • ...
Page 70
Development Tools Support WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Home Office Aisys U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte Craft ...
Page 71
... Physical Dimensions inches (millimeters) unless otherwise noted Order Number COP87L88EBV-XE or COP87L88RBV-XE Order Number COP87L89EBV-XE or COP87L89RBV-XE 44-Lead Molded Plastic Leaded Chip Carrier NS Plastic Chip Package Number V44A 68-Lead Molded Plastic Leaded Chip Carrier NS Plastic Chip Package Number V68A 71 www.national.com ...
Page 72
... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...