cop87l88rb National Semiconductor Corporation, cop87l88rb Datasheet - Page 18

• Manufacturer Part Number: cop87l88rb
• Description: 8-bit Cmos Otp Microcontrollers With 16k Or 32k Memory, Can Interface, 8-bit A/d, And Usart
• Manufacturer: National Semiconductor Corporation

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Multi-Input Wakeup
The GIE (global interrupt enable) bit enables the interrupt
function. A control flag, LPEN, functions as a global interrupt
enable for Port L interrupts. Setting the LPEN flag will enable
interrupts and vice versa. A separate global pending flag is
not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart ex-
ecution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the in-
terrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immedi-
ately since crystal oscillators or ceramic resonators have a fi-
PORT M INTERRUPTS
Port M provides the user with seven fully selectable, edge
sensitive interrupts which are all vectored into the same ser-
vice subroutine.
The interrupt from Port M shares logic with the wake up cir-
cuitry. The MWKEN register allows interrupts from Port M to
be individually enabled or disabled. The MWKEDG register
specifies the trigger condition to be either a positive or a
negative edge. The MWKPND register latches in the pend-
ing trigger conditions.
The LPEN control flag in the ICNTRL register functions as a
global interrupt enable for Port M interrupts. Setting the
LPEN flag enables interrupts. Note that the GIE bit in the
PSW register must also be set to enable these Port L inter-
rupts. A global pending flag is not needed since each pin has
a corresponding pending flag in the MWKPND register.
Since Port M is also used for exiting the device from the
HALT or IDLE mode, the user can elect to exit the HALT or
IDLE mode either with or without the interrupt enabled. If the
user elects to disable the interrupt, then the device restarts
execution from the point at which it was stopped (first in-
(Continued)
FIGURE 13. Port L Multi-Input Wake-Up Logic
18
nite start up time. The IDLE Timer (T0) generates a fixed de-
lay to ensure that the oscillator has indeed stabilized before
allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator cir-
cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is
loaded with a value of 256 and is clocked from the t
tion cycle clock. The t
oscillator clock by a factor of 10. A Schmitt trigger following
the CKI on-chip inverter ensures that the IDLE timer is
clocked only when the oscillator has a sufficiently large am-
plitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
start-up time-out from the IDLE timer enables the clock sig-
nals to be routed to the rest of the chip.
struction cycle of the instruction following the enter HALT or
IDLE mode instruction). In the other case, the device finishes
the instruction which was being executed when the part was
stopped (the NOP(Note *NO TARGET FOR FNXref
NS9529*) instruction following the enter HALT or IDLE mode
instruction), and then branches to the interrupt service rou-
tine. The device then reverts to normal operation.
Note 16: The user must place two NOPs after an enter HALT or IDLE mode
instruction.
To prevent erroneous clearing of the SPI receive FIFO when
entering HALT/IDLE mode, the user needs to enable the
MIWU on port M3. (SS) by setting bit 3 in the MWKEN reg-
ister.
CAN RECEIVE WAKEUP
The CAN Receive Wakeup source can be enabled or dis-
abled. There is no specific enable bit for the CAN Wakeup
feature. Although the wakeup feature on pins L0..17 and
M0..M7 can be programmed to generate an interrupt (Port L
or Port M interrupt), no interrupt is generated upon a CAN re-
c
clock is derived by dividing down the
DS100044-14
c
instruc-