cop87l88rb National Semiconductor Corporation, cop87l88rb Datasheet - Page 20

• Manufacturer Part Number: cop87l88rb
• Description: 8-bit Cmos Otp Microcontrollers With 16k Or 32k Memory, Can Interface, 8-bit A/d, And Usart
• Manufacturer: National Semiconductor Corporation

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CAN Interface Block
Functional Block Description of
the CAN Interface
Interface Management Logic (IML)
The IML executes the CPU’s transmission and reception
commands and controls the data transfer between CPU,
Rx/Tx and CAN registers. It provides the CAN Interface with
Rx/Tx data from the memory mapped Register Block. It also
sets and resets the CAN status information and generates
interrupts to the CPU.
Bit Stream Processor (BSP)
The BSP is a sequencer controlling the data stream between
The Interface Management Logic (parallel data) and the bus
line (serial data). It controls the transceive logic with regard
to reception and arbitration, and creates error signals ac-
cording to the bus specification.
(Continued)
FIGURE 14. CAN Interface Block Diagram
20
Transceive Logic (TCL)
The TCL is a state machine which incorporates the bit stuff
logic and controls the output drivers, CRC logic and the
Rx/Tx shift registers. It also controls the synchronization to
the bus with the CAN clock signal generated by the BTL.
Error Management Logic (EML)
The EML is responsible for the fault confinement of the CAN
protocol. It is also responsible for changing the error
counters, setting the appropriate error flag bits and interrupts
and changing the error status (passive, active and bus off).
Cyclic Redundancy Check (CRC)
Generator and Register
The CRC Generator consists of a 15-bit shift register and the
logic required to generate the checksum of the destuffed bit-
stream. It informs the EML about the result of a receiver
checksum.
The checksum is generated by the polynomial:
15
+
14
+
10
+
DS100044-16
8
+
7
+
4
+
3
− 1