cop888ek National Semiconductor Corporation, cop888ek Datasheet - Page 14

• Manufacturer Part Number: cop888ek
• Description: 8-bit Cmos Rom Based Microcontrollers With 8k Memory, Comparator, And Single-slope A/d Capability
• Manufacturer: National Semiconductor Corporation

www.national.com
Pin Descriptions
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Port G has the following alternate features:
Port G has the following dedicated functions:
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredicatable values.
PORT I is an eight-bit Hi-Z input port. The 28-pin device does
not have a full complement of Port I pins. The unavailable
pins are not terminated i.e., they are floating. A read opera-
tion for these unterminated pins will return unpredictable val-
ues. The user must ensure that the software takes this into
account by either masking or restricting the accesses to bit
operations. The unterminated Port I pins will draw power
only when addressed.
Port I is an eight-bit Hi-Z input port.
Port I0–I7 are used for the analog function block.
The Port I has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
G7 CKO Oscillator dedicated output or general purpose
G1 WDOUT WATCHDOG and/or Clock Monitor dedi-
I7
I6
G7
G6
COMPOUT (Comparator Output)
COMPIN5+ (Comparator Positive Input 5)
input
cated output
CLKDLY
Alternate SK
Config Reg.
(Continued)
HALT
IDLE
Data Reg.
FIGURE 4. I/O Port Configurations
14
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (ex-
cept D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
Functional Description
The architecture of the device is modified Harvard architec-
ture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
I5
I4
I3
I2
I1
I0
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
ternal loads on this pin must ensure that the output voltages stay
above 0.8 V
keep the external loading on D2 to
COMPIN4+ (Comparator Positive Input 4)
COMPIN3+ (Comparator Positive Input 3)
COMPOUT/COMPIN2+
Comparator Positive Input 2))
COMPIN0+ (Comparator Positive Input 0)
COMPIN−
Source Out)
COMPIN1+ (Comparator Positive Input 1)
CC
to prevent the chip from entering special modes. Also
DS012094-5
(Comparator
c
) cycle time.
<
1000 pF.
(Comparator
Negative
Input/Current
Output/