cop888ek National Semiconductor Corporation, cop888ek Datasheet - Page 6

• Manufacturer Part Number: cop888ek
• Description: 8-bit Cmos Rom Based Microcontrollers With 8k Memory, Comparator, And Single-slope A/d Capability
• Manufacturer: National Semiconductor Corporation

www.national.com
Input Capacitance
Load Capacitance on D2
Instruction Cycle Time (t
Inputs
Output Propagation Delay (Note 7)
MICROWIRE
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
Input Pulse Width (Note 8)
Reset Pulse Width
DC Electrical Characteristics 98xEK:
AC Electrical Characteristics 98xEK:
Note 2: t
Note 3: Maximum rate of voltage change must be
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to V
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal
clock mode.
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
biased at voltages
pins will not latch up. The voltage at the pins must be limited to
cludes ESD transients.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8: Parameter characterized but not tested.
0˚C
0˚C
Crystal, Resonator,
R/C Oscillator
t
t
t
SO, SK
All Others
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
SETUP
HOLD
PD1
, t
T
T
PD0
c
A
A
= Instruction Cycle Time
+ 70˚C unless otherwise specified
+ 70˚C unless otherwise specified
™
Setup Time (t
Parameter
>
V
Parameter
CC
(the pins do not have source current when biased at a voltage below V
c
)
UWH
UWS
) (Note 7)
) (Note 7)
<
UPD
0.5 V/ms.
)
<
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
4.0V
2.5V
4.0V
2.5V
4.0V
2.5V
4.0V
2.5V
R
4.0V
2.5V
4.0V
2.5V
V
V
V
CC
CC
CC
L
= 2.2k, C
Conditions
4.0V
4.0V
4.0V
V
V
V
V
V
V
V
V
V
V
V
V
Conditions
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
(Continued)
6
<
<
<
<
<
<
L
6.0V
6.0V
6.0V
6.0V
6.0V
6.0V
4.0V
4.0V
4.0V
4.0V
= 100 pF
4.0V
4.0V
CC
). The effective resistance to V
>
Min
200
500
150
1.0
2.5
3.0
7.5
1.0
1.0
1.0
1.0
1.0
60
20
56
V
CC
Min
DD
and the pins will have sink current to V
HALT is done with device neither sourcing nor
Typ
Typ
CC
is 750
Max
1.75
220
DC
DC
DC
DC
0.7
2.5
1000
1
Max
7
(typical). These two
CC
Units
Units
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
µs
t
t
t
t
when
c
c
c
c
pF
pF
CC
CC
;