cop8cfe9 National Semiconductor Corporation, cop8cfe9 Datasheet - Page 17

• Manufacturer Part Number: cop8cfe9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, And 10-bit A/d
• Manufacturer: National Semiconductor Corporation

4.0 Functional Description
Example: The following sets a value in the Option Register
and User Identification for a COP8CFE9HVA7. The Option
Register bit values shown select options: Security disabled,
WATCHDOG enabled HALT mode enabled and execution
will commence from Flash Memory.
Note: All programmers certified for programming this family
of parts will support programming of the Option Register.
Please contact National or your device programmer supplier
for more information.
4.6 SECURITY
The device has a security feature which, when enabled,
prevents external reading of the Flash program memory. The
security bit in the Option Register determines, whether se-
curity is enabled or disabled. If the security feature is dis-
abled, the contents of the internal Flash Memory may be
read by external programmers or by the built in
MICROWIRE/PLUS serial interface ISP. Security must be
enforced by the user when the contents of the Flash
Memory are accessed via the user ISP or Virtual EE-
PROM capability.
If the security feature is enabled, then any attempt to exter-
nally read the contents of the Flash Memory will result in the
value FF (hex) being read from all program locations (except
the Option Register). In addition, with the security feature
enabled, the write operation to the Flash program memory
and Option Register is inhibited. Page Erases are also inhib-
ited when the security feature is enabled. The Option Reg-
ister is readable regardless of the state of the security bit by
accessing location FFFF (hex). Mass Erase Operations are
possible regardless of the state of the security bit.
The security bit can be erased only by a Mass Erase of the
entire contents of the Flash unless Flash operation is under
the control of User ISP functions.
Note: The actual memory address of the Option Register is
0x1FFF (hex), however the MICROWIRE/PLUS ISP routines
require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
The entire Option Register must be programmed at one time
and cannot be rewritten without first erasing the entire last
page of Flash Memory.
4.7 RESET
The device is initialized when the RESET pin is pulled low.
.chip
.sect
.db
.endsect
...
.end
.endsect
8CFE
option, conf
0x01
start
FIGURE 8. Reset Logic
;wd, halt, flex
;options
20026411
(Continued)
17
The following occurs upon initialization:
Port A: TRI-STATE (High Impedance Input)
Port B: TRI-STATE (High Impedance Input)
Port H: TRI-STATE (High Impedance Input)
Port L: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
T2CNTRL: CLEARED
HSTCR: CLEARED
ITMR: Cleared except Bit 6 = 1
Accumulator, Timer 1 and Timer 2:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
S Register: CLEARED
RAM:
ANALOG TO DIGITAL CONVERTER:
ISP CONTROL:
WATCHDOG (if enabled):
Port G: TRI-STATE (High Impedance Input). Exceptions: If
Watchdog is enabled, then G1 is Watchdog output. G0
and G2 have their weak pull-up enabled during RESET.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Moni-
tor bit set. The WATCHDOG and Clock Monitor circuits
are inhibited during reset. The WATCHDOG service win-
dow bits being initialized high default to the maximum
WATCHDOG service window of 64k T0 clock cycles. The
Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached
the minimum specified frequency at the termination of
reset. A Clock Monitor error will cause an active low error
output on pin G1. This error output will continue until
16–32 T0 clock cycles following the clock frequency
reaching the minimum specified value, at which time the
G1 output will go high.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Moni-
tor bit set. The WATCHDOG and Clock Monitor circuits
are inhibited during reset. The WATCHDOG service win-
dow bits being initialized high default to the maximum
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
ENAD: CLEARED
ADRSTH: RANDOM
ADRSTL: RANDOM
ISPADLO: CLEARED
ISPADHI: CLEARED
PGMTIM: PRESET TO VALUE FOR 10 MHz CKI
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