cop8cfe9 National Semiconductor Corporation, cop8cfe9 Datasheet - Page 30

• Manufacturer Part Number: cop8cfe9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, And 10-bit A/d
• Manufacturer: National Semiconductor Corporation

www.national.com
6.0 Timers
register. Any type of read/write operation, including SBIT and
RBIT may be performed on this register in any operating
mode.
7.0 Power Saving Features
Today, the proliferation of battery-operated based applica-
tions has placed new demands on designers to drive power
consumption down. Battery-operated systems are not the
only type of applications demanding low power. The power
budget constraints are also imposed on those consumer/
industrial applications where well regulated and expensive
power supply costs cannot be tolerated. Such applications
rely on low cost and low power supply voltage derived di-
rectly from the “mains” by using voltage rectifier and passive
components. Low power is demanded even in automotive
applications, due to increased vehicle electronics content.
This is required to ease the burden from the car battery. Low
power 8-bit microcontrollers supply the smarts to control
battery-operated, consumer/industrial, and automotive appli-
cations.
The device offers system designers a variety of low-power
consumption features that enable them to meet the demand-
ing requirements of today’s increasing range of low-power
applications. These features include low voltage operation,
low current drain, and power saving features such as HALT,
IDLE, and Multi-Input Wake-Up (MIWU).
The device offers the user two power save modes of opera-
tion: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board os-
cillator circuitry and timer T0 are active but all other micro-
controller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
Clock Monitor, if enabled, can be active in both modes.
Mode
1
2
3
TxC3
1
1
0
0
0
1
0
1
(Continued)
TxC2
0
0
0
0
1
1
1
1
TxC1
1
0
0
1
0
0
1
1
TABLE 16. Timer Operating Modes
PWM: TxA Toggle
PWM: No TxA
Toggle
External Event
Counter
External Event
Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
Captures:
TxA Pos. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Pos. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
Description
30
7.1 HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCH-
DOG logic on the device is disabled during the HALT mode.
However, the clock monitor circuitry, if enabled, remains
active and will cause the WATCHDOG output pin (WDOUT)
to go low. If the HALT mode is used and the user does not
want to activate the WDOUT pin, the Clock Monitor should
be disabled after the device come out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register).
The device supports two different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wake-up feature on Port L. The second method
is by pulling the RESET pin low.
On wake-up from Port L, the device resumes execution from
the HALT point. On wake-up from RESET execution will
resume from location PC=0 and all RESET conditions apply.
If a crystal or ceramic resonator is selected as the oscillator,
the Wake-up signal is not allowed to start the chip running
immediately since crystal oscillators and ceramic resonators
have a delayed start up time to reach full amplitude and
frequency stability. The IDLE timer is used to generate a
fixed delay to ensure that the oscillator has indeed stabilized
before allowing instruction execution. In this case, upon
detecting a valid Wake-up signal, only the oscillator circuitry
is enabled. The IDLE timer is loaded with a value of 256 and
is clocked with the t
derived by dividing the oscillator clock down by a factor of 9.
The Schmitt trigger following the CKI inverter on the chip
ensures that the IDLE timer is clocked only when the oscil-
Autoreload RA
Autoreload RA
Timer Underflow
Timer Underflow
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Interrupt A
Source
C
instruction cycle clock. The t
Autoreload RB
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Pos. TxB Edge
Neg. TxB
Edge
Pos. TxB
Edge
Neg. TxB
Edge
Interrupt B
Source
t
t
TxA Pos.
Edge
TxA Neg.
Edge
t
t
t
t
C
C
C
C
C
C
Counts On
or MCLK
or MCLK
or MCLK
or MCLK
or MCLK
or MCLK
C
Timer
clock is