cop8cfe9 National Semiconductor Corporation, cop8cfe9 Datasheet - Page 50

• Manufacturer Part Number: cop8cfe9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, And 10-bit A/d
• Manufacturer: National Semiconductor Corporation

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13.0 Instruction Set
Register B or X Indirect with Post-Incrementing/
Decrementing. The relevant memory address is specified
by the contents of the B Register or X register (pointer
register). The pointer register is automatically incremented
or decremented after execution, allowing easy manipulation
of memory blocks with software loops. In assembly lan-
guage, the notation [B+], [B−], [X+], or [X−] specifies which
register serves as the pointer, and whether the pointer is to
be incremented or decremented.
Example: Exchange Memory with Accumulator, B Indirect
Intermediate. The data for the operation follows the instruc-
tion opcode in program memory. In assembly language, the
number sign character (#) indicates an immediate operand.
Example: Load Accumulator Immediate
Immediate Short. This is a special case of an immediate
instruction. In the “Load B immediate” instruction, the 4-bit
immediate value in the instruction is loaded into the lower
nibble of the B register. The upper nibble of the B register is
reset to 0000 binary.
Example: Load B Register Immediate Short
Indirect from Program Memory. This is a special case of
an indirect instruction that allows access to data tables
stored in program memory. In the “Load Accumulator Indi-
rect” (LAID) instruction, the upper and lower bytes of the
Program Counter (PCU and PCL) are used temporarily as a
pointer to program memory. For purposes of accessing pro-
gram memory, the contents of the Accumulator and PCL are
exchanged. The data pointed to by the Program Counter is
loaded into the Accumulator, and simultaneously, the original
contents of PCL are restored so that the program can re-
sume normal execution.
Example: Load Accumulator Indirect
Memory Location
Memory Location
Accumulator
Accumulator
Accumulator
with Post-Increment
X A,[B+]
LD A,#05
LD B,#7
Reg/Data
0005 Hex
Reg/Data
0005 Hex
Reg/Data
Reg/Data
B Pointer
B Pointer
B Pointer
Memory
Memory
Memory
Memory
Contents
Contents
Before
12 Hex
XX Hex
Before
Contents
Contents
01 Hex
87 Hex
05 Hex
03 Hex
62 Hex
05 Hex
Before
Before
(Continued)
Contents
Contents
07 Hex
05 Hex
Contents
Contents
After
After
87 Hex
01 Hex
05 Hex
62 Hex
03 Hex
06 Hex
After
After
50
13.3.2 Tranfer-of-Control Addressing Modes
Program instructions are usually executed in sequential or-
der. However, Jump instructions can be used to change the
normal execution sequence. Several transfer-of-control ad-
dressing modes are available to specify jump addresses.
A change in program flow requires a non-incremental
change in the Program Counter contents. The Program
Counter consists of two bytes, designated the upper byte
(PCU) and lower byte (PCL). The most significant bit of PCU
is not used, leaving 15 bits to address the program memory.
Different addressing modes are used to specify the new
address for the Program Counter. The choice of addressing
mode depends primarily on the distance of the jump. Farther
jumps sometimes require more instruction bytes in order to
completely specify the new Program Counter contents.
The available transfer-of-control addressing modes are:
• Jump Relative
• Jump Absolute
• Jump Absolute Long
• Jump Indirect
The transfer-of-control addressing modes are described be-
low. Each description includes an example of a Jump in-
struction using a particular addressing mode, and the effect
on the Program Counter bytes of executing that instruction.
Jump Relative. In this 1-byte instruction, six bits of the
instruction opcode specify the distance of the jump from the
current program memory location. The distance of the jump
can range from −31 to +32. A JP+1 instruction is not allowed.
The programmer should use a NOP instead.
Example: Jump Relative
Jump Absolute. In this 2-byte instruction, 12 bits of the
instruction opcode specify the new contents of the Program
Counter. The upper three bits of the Program Counter re-
main unchanged, restricting the new Program Counter ad-
dress to the same 4-kbyte address space as the current
instruction. (This restriction is relevant only in device using
more than one 4-kbyte program memory space.)
Example: Jump Absolute
Memory Location
Accumulator
LAID
JP 0A
JMP 0125
Reg/Data
041F Hex
Memory
PCU
PCU
PCU
PCL
PCL
PCL
Reg
Reg
Contents
Contents
0C Hex
02 Hex
05 Hex
77 Hex
Before
Before
Contents
1F Hex
Before
04 Hex
35 Hex
25 Hex
Contents
Contents
02 Hex
0F Hex
01 Hex
25 Hex
After
After
Contents
04 Hex
36 Hex
25 Hex
25 Hex
After