r5f3650kcnfb Renesas Electronics Corporation., r5f3650kcnfb Datasheet - Page 106

• Manufacturer Part Number: r5f3650kcnfb
• Description: M16c/65c Group Renesas Mcu
• Manufacturer: Renesas Electronics Corporation.

M16C/65C Group
R01DS0015EJ0100 Rev.1.00
Feb 07, 2011
Switching Characteristics
(V
Table 5.63
Notes:
CC1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD
h(RD-AD
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
d(DB-WR)
h(WR-DB)
5.3.4.5
1.
2.
3.
4.
5.
Symbol
= V
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − V
by a circuit of the right figure.
For example, when V
of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2V
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
)
CC2
This standard value shows the timing when the output is off, and
= 6.7 ns.
)
)
m 10
------------------ - 15 ns
m 10
------------------ - 25 ns
n 10
----------------- - 40 ns
f
f
f
m
------------------ -
f
(
(
(
(
BCLK
BCLK
BCLK
×
BCLK
×
×
= 3 V, V
×
10
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1
to 3 Recovery Cycles and Accessing External Area
Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2φ + 3φ, 2φ +
4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1 to 3 Recovery Cycles and Accessing External
Area)
9
9
9
)
)
)
9
)
–
–
–
+
0 ns
SS
[
[
[
[
OL
= 0 V, at T
]
]
]
]
/V
OL
CC2
= 0.2V
)
CC2
CC2
opr
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
/V
, C = 30 pF, R = 1 kΩ, hold time
= -20°C to 85°C/-40°C to 85°C unless otherwise specified)
Parameter
CC2
)
(3)
Figure 5.29
Measuring
Condition
See
DBi
(Note 4)
(Note 2)
(Note 1)
(Note 5)
Min.
5. Electrical Characteristics
-4
0
0
0
0
Standard
V
CC1
Max.
= V
30
30
25
30
30
40
Page 106 of 109
C
R
CC2
= 3 V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns