m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 54

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S
the transmission data is not output). When data is written to the
transmit buffer register in this state, data starts to be shifted to the
transmit shift register. When the serial I/O enable bit is set to “1” at
this time, the data during internally shifting is output to the TxD pin
and an operation failure occurs.
1.2 Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O enable bit to “0” (serial I/O disabled).
1.3 Stop of transmit/receive operation
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and re-
ception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clear-
ing the serial I/O enable bit to “0” (serial I/O disabled) (refer to
1.1).
54
Note
Note
Note
Reason
Reason
Notes concerning serial I/O1
CLK
, and S
RDY
function as I/O ports,
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S
the transmission data is not output). When data is written to the
transmit buffer register in this state, data starts to be shifted to the
transmit shift register. When the serial I/O enable bit is set to “1” at
this time, the data during internally shifting is output to the TxD pin
and an operation failure occurs.
2.2 Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
Clear the transmit enable bit to “0” (transmit disabled).
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S
the transmission data is not output). When data is written to the
transmit buffer register in this state, data starts to be shifted to the
transmit shift register. When the serial I/O enable bit is set to “1” at
this time, the data during internally shifting is output to the TxD pin
and an operation failure occurs.
Clear the receive enable bit to “0” (receive disabled).
Note
Reason
Note
Note 1 (only transmission operation is stopped)
Reason
Note 2 (only receive operation is stopped)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLK
CLK
3803/3804 Group
, and S
, and S
RDY
RDY
function as I/O ports,
function as I/O ports,