m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 73

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

[I
The I
munication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of S2, address 0015
BC0 to BC2 are returned to “000
Also when a START condition is received, these bits become
“000
8 bits.
•Bit 3: I
This bit enables to use the multi-master I
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I
• Writing data to the I
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “I
ceived, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I
registers 0 to 2 are compared with address data. When this bit is
set to “1,” the 10-bit addressing format is selected, and all the bits
of the I
dress data.
•Bit 7: I
This bit selects the input level of the SCL and SDA pins of the
multi-master I
status register, S1, at address 0013
disabled.
2
C Control Register (S1D)] 0014
2
2
” and the address data is always transmitted and received in
C control register (S1D: address 0014
2
2
2
C slave address registers 0 to 2 are compared with ad-
C interface enable bit (ES0)
C-BUS interface pin input level selection bit (TISS)
2
C-BUS interface.
2
C interrupt request signal occurs immediately
2
C data shift register (S0: address 0011
2
2
C Status Register,” bit 1) is re-
”.
16
16
) have been transferred, and
).
2
C-BUS interface. When
16
) controls data com-
16
2
C slave address
16
) is
2
C
Fig. 67 Structure of I
T I S S
b 7
1 0 B I T
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
S A D
ALS ES0 BC2 B C 1 B C 0
MITSUBISHI MICROCOMPUTERS
2
C control register
3803/3804 Group
b0
I
( S 1 D : a d d r e s s 0 0 1 4
B i t c o u n t e r ( N u m b e r o f
t r a n s m i t / r e c e i v e b i t s )
I
e n a b l e b i t
D a t a f o r m a t s e l e c t i o n b i t
Addressing format
selection bit
Not used
(return “0” when read)
I
level selection bit
2
2
2
C c o n t r o l r e g i s t e r
C - B U S i n t e r f a c e
b 2 b 1 b 0
C-BUS interface pin input
0
0
0
0
1
1
1
1
0 : D i s a b l e d
1 : E n a b l e d
0 : A d d r e s s i n g f o r m a t
1 : F r e e d a t a f o r m a t
0 : 7-bit addressing
1 : 10-bit addressing
0 : CMOS input
1 : SMBUS input
format
format
0
0
1
1
0
0
1
1
0 : 8
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
1 6
)
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