m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 83

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I
• I
• I
• I
• I
• I
• I
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generat-
2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag
3. Use “STA $12, STX $12” or “STY $12” of the zero page ad-
4. Execute the branch instruction of above 2 and the store instruc-
2
C-BUS interface are described below.
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
0FF7
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
The read-modify-write instruction can be executed for this regis-
ter.
0016
The read-modify-write instruction can be executed for this regis-
ter.
Precautions when using multi-master I
BUS interface
ing procedure are described as the following 2 to 5.
BUSFREE:
BUSBUSY:
confirming and branch process.
dressing instruction for writing the slave address value to the
I
tion of above 3 continuously shown the above procedure
example.
2
2
2
2
2
2
2
C data shift register (S0: address 0011
C status register (S1: address 0013
C control register (S1D: address 0014
C clock control register (S2: address 0015
C slave address registers 0 to 2 (S0D0 to S0D2: addresses
C START/STOP condition control register (S2D: address
LDA —
SEI
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
STA S0
LDM #$F0, S1
CLI
CLI
C data shift register.
: :
: :
: :
16
16
)
to0FF9
16
)
(Taking out of slave address value)
(Interrupt disabled)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
(Interrupt enabled)
16
)
16
16
)
)
16
)
2
C-
5. Disable interrupts during the following three process steps:
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions of the generat-
2. Select the slave receive mode when the PIN bit is “0.” Do not
3. The SCL pin is released by writing the slave address value to
4. Disable interrupts during the following two process steps:
(4) Writing to I
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simulta-
neously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” It is because
it may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I
tus register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers does not have the problem.
• Writing of slave address value
• Trigger of RESTART condition generating
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
ing procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is “0.”
write “1” to the PIN bit. Neither “0” nor “1” is specified for the
writing to the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
the I
LDM #$00, S1
LDA —
SEI
STA S0
LDM #$F0, S1
CLI
: :
: :
2
C data shift register.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
C status register
MITSUBISHI MICROCOMPUTERS
2
C data shift register S0 and the I
(Select slave receive mode)
(Taking out of slave address value)
(Interrupt disabled)
(Writing of slave address value)
(Trigger of RESTART condition generating)
(Interrupt enabled)
3803/3804 Group
2
C sta-
83