km416s1120d ETC-unknow, km416s1120d Datasheet
km416s1120d
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km416s1120d Summary of contents
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... KM416S1120D SDRAM 512K x 16bit x 2 Banks Samsung Electronics reserves the right to change products or specification without notice. Synchronous DRAM LVTTL Revision 1.4 June 1999 - 1 - CMOS SDRAM Rev. 1.4 (Jun. 1999) ...
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... Revision 1.0 (February 1999) - Final • Changed tRDL of KM416S1120D-6 @ CL3 from 2CLK to 1CLK • Changed tRAS and tRC of KM416S1120D-7 @ CL2 from 6CLK and 8CLK to 5CLK and 7CLK each. • Changed tSAC and tSHZ of KM416S1120D-7 @ CL3 from 6ns to 5.5ns • Changed tOH of KM416S1120D-8/10 from 3ns to 2.5ns • ...
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... LCBR CLK CKE GENERAL DESCRIPTION The KM416S1120D is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits, fabricated with SAMSUNG s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... KM416S1120D PIN CONFIGURATION (TOP VIEW) A10/AP PIN FUNCTION DESCRIPTION Pin Name CLK System Clock CS Chip Select CKE Clock Enable /AP Address Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQM Data Input/Output Mask DQ ~ Data Input/Output ...
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... V (min) = -2.0V AC. The undershoot voltage duration Any input DDQ Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of KM416S1120D-C/6 is 3.135V~3.6V. CAPACITANCE (V = 3.3V Pin Clock RAS, CAS, WE, CS, CKE, L(U)DQM Address ...
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... I CC6 Note : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. KM416S1120DT-G** 5. KM416S1120DT-F Test Condition Burst Length = (min) ...
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... Output load condition 3.3V 1200 Output 50pF 870 (Fig Output Load Circuit Note : 1. The DC/AC Test Output Load of KM416S1120D-C/6/7 is 30pF. 2. The VDD condition of KM416S1120D-C/6 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter CAS Latency CLK cycle time Row active to row active delay ...
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... KM416S1120D Parameter CLK cycle time Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change case of row precharge interrupt, auto precharge and read burst stop. ...
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... KM416S1120D SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable ...
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... KM416S1120D MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA A /AP 10 Function RFU RFU W.B.L Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 1 Reserved Write Burst Length Length Burst 1 Single Bit POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= " ...
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... KM416S1120D BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address ...
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... KM416S1120D DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...
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... KM416S1120D DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The ...
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... KM416S1120D DEVICE OPERATIONS (Continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle ...
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... KM416S1120D BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) CLK CMD WR CKE Internal CKE DQ(CL2 DQ(CL3 Not Written 2. DQM Operation 1) Write Mask (BL=4) CLK WR CMD DQM DQ(CL2 DQ(CL3 DQM to Data-in Mask = 0 ...
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... KM416S1120D 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note ADD tCDL Note 3 *Note : 1. By " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... KM416S1120D 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note ADD tCDL Note 3 *Note : 1. By " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... KM416S1120D ( Continued ) (b) CL=3, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iii) CMD DQM DQ iv) CMD RD DQM DQ 5. Write Interrupted by Precharge & DQM CLK WR CMD DQM *Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. ...
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... KM416S1120D 6. Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 7. Auto Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) *Note : Last data in to row precharge delay RDL 2. Number of valid output data after row precharge : for CAS Latency = respectively. ...
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... KM416S1120D 8. Burst Stop & Interrupted by Precharge 1) Normal Write (BL=4) CLK CMD WR DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS 1) Mode Register Set CLK Note 4 CMD PRE tRP *Note : CLK RDL CLK ; Last data in to burst stop delay. ...
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... KM416S1120D 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK CMD 11. Auto Refresh & Self Refresh 1) Auto Refresh & Self Refresh Note 3 CLK Note 4 CMD PRE CKE tRP 2) Self Refresh Note 6 CLK ...
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... KM416S1120D 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic MODE 4 8 Full Page Special BRSW MODE Random Burst Stop MODE RAS Interrupt (Interrupted by Precharge) Interrupt ...
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... KM416S1120D FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State IDLE Row Active Read ...
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... KM416S1120D FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State Row Activating Refreshing Mode Register Accessing Abbreviations : RA = Row Address NOP = No Operation Command *Note : 1 ...
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... KM416S1120D FUNCTION TRUTH TABLE (TABLE 2) CKE Current CKE CS n State (n- Self Refresh All Banks Precharge Power Down All ...
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... KM416S1120D Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH CLOCK tCC CKE *Note 1 CS tRCD tSH RAS tSS tSH CAS tSS tSH ADDR Ra Ca tSS *Note 2 *Note 2 /AP Ra *Note 3 10 tRAC DQ WE DQM Row Active ...
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... KM416S1120D *Note : 1. All inputs expect CKE & DQM can be don 2. Bank active & read/write are controlled by BA Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/ A10/AP and BA control bank precharge when precharge command is asserted. ...
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... KM416S1120D Power Up Sequence CLOCK CKE High level is necessary CS tRP RAS CAS ADDR BA A /AP 10 High DQM High level is necessary Precharge Auto Refresh (All Banks tRC Auto Refresh - 28 CMOS SDRAM tRC Key RAa ...
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... KM416S1120D Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD RAS CAS ADDR Ra Ca0 CL=2 tRAC *Note 3 CL=3 tRAC *Note 3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. ...
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... KM416S1120D Page Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD RAS CAS ADDR Ra Ca0 CL=2 CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention ...
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... KM416S1120D Page Read Cycle at Different Bank @Burst Length CLOCK CKE *Note 1 CS RAS CAS RAa CAa RBb ADDR BA A /AP RAa RBb 10 DQ CL=2 CL=3 WE DQM Row Active Row Active (A-Bank) (B-Bank) Read (A-Bank) *Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. ...
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... KM416S1120D Page Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS ADDR RAa CAa BA A /AP RAa 10 DQ DAa0 DAa1 DAa2 WE DQM Row Active Row Active (A-Bank) Write (A-Bank) *Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. ...
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... KM416S1120D Read & Write Cycle at Different Bank @Burst Length CLOCK CKE CS RAS CAS RAa CAa ADDR BA A /AP RAa 10 DQ CL=2 CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. t should be met to complete write. CDL HIGH RBb RBb QAa0 QAa1 QAa2 QAa3 ...
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... KM416S1120D Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE CS RAS CAS ADDR / CL=2 CL=3 WE DQM Read with Row Active Auto Pre (A-Bank) (A-Bank) Row Active (B-Bank) *Note: * When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. ...
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... KM416S1120D Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE CS RAS CAS ADDR / CL=2 CL=3 WE DQM Row Active Auto Precharge (A-Bank) *Note : * Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point ...
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... KM416S1120D Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length CLOCK CKE CS RAS CAS ADDR / DQM Row Active Read *Note : 1. DQM is needed to prevent bus contention Qa0 Qa1 Qa2 Qa3 tSHZ ...
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... KM416S1120D Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page CLOCK CKE CS RAS CAS RAa CAa ADDR BA A /AP RAa 10 DQ CL=2 CL=3 WE DQM Row Active Read (A-Bank) (A-Bank) *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. ...
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... KM416S1120D Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page CLOCK CKE CS RAS CAS ADDR RAa CAa BA RAa A / DAa0 DAa1 DAa2 DAa3 DAa4 WE DQM Row Active Write (A-Bank) (A-Bank) *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. ...
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... KM416S1120D Burst Read Single bit Write Cycle @Burst Length CLOCK *Note 1 CKE CS RAS CAS ADDR RAa CAa BA A /AP RAa 10 DQ CL=2 DAa0 CL=3 DAa0 WE DQM Row Active Row Active (A-Bank) Write (A-Bank) *Note : 1. BRSW modes is enabled by setting A At the BRSW Mode, the burst length at write is fixed to "1" regaredless of programmed burst length. ...
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... KM416S1120D Active/Precharge Power Down Mode @CAS Latency=2, Burst Length CLOCK tSS *Note 1 CKE *Note 3 CS RAS CAS ADDR DQM Precharge Power-down Entry *Note : 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. ...
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... KM416S1120D Self Refresh Entry & Exit Cycle CLOCK *Note 2 *Note 1 CKE tSS CS RAS CAS ADDR BA A / DQM Self Refresh Entry *Note : TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. ...
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... KM416S1120D Mode Register Set Cycle CLOCK HIGH CKE CS *Note 2 RAS *Note 1 CAS *Note 3 ADDR Key Ra DQ Hi-Z WE DQM MRS New Command * Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & ...
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... KM416S1120D PACKAGE DIMENSIONS 50-TSOP2-400CF #50 #1 0.10MAX [ ] 0.075MAX +0.10 (0.875) 0.30 -0.05 #26 #25 20.95 0.10 0.80TYP +0.10 [0.80 0.08] 0.05MIN 0.35 -0. CMOS SDRAM Unit : Millimeters 0~8 0.25 TYP +0.075 0.125 -0.035 1.20MAX 1.00 0.10 Rev. 1.4 (Jun. 1999) ...