km416s1120d ETC-unknow, km416s1120d Datasheet - Page 29

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

DQ
CLOCK
KM416S1120D
Read & Write Cycle at Same Bank @Burst Length=4
A
ADDR
10
DQM
CKE
RAS
CAS
/AP
WE
CS
BA
CL=2
CL=3
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
0
Row Active
(A-Bank)
Ra
Ra
1
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
3. Access time from Row active command. t
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst wrap-around).
is available after Row precharge. Last valid output will be Hi-Z(t
2
tRCD
*Note 3
tRAC
3
(A-Bank)
*Note 3
tRAC
Read
Ca0
4
5
Qa0
tSAC
6
tRC
Qa1
Qa0
tOH
*Note 1
tSAC
7
CC
Qa2
Qa1
tOH
*Note 2
*(t
8
Precharge
(A-Bank)
RCD
Qa3
Qa2
- 29
+ CAS latency - 1) + t
9
HIGH
Qa3
tSHZ
10
*Note 4
tSHZ
SHZ
11
Row Active
(A-Bank)
) after the clcok.
Rb
Rb
*Note 4
12
SAC
13
(A-Bank)
Write
Cb0
Db0
Db0
14
Db1
Db1
15
CMOS SDRAM
Db2
Db2
Rev. 1.4 (Jun. 1999)
16
Db3
Db3
17
Precharge
(A-Bank)
tRDL
tRDL
18
: Don't care
19