km416s1120d ETC-unknow, km416s1120d Datasheet - Page 41

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

CLOCK
KM416S1120D
Self Refresh Entry & Exit Cycle
A
ADDR
10
DQM
CKE
RAS
CAS
/AP
WE
DQ
CS
BA
*Note :
0
Self Refresh Entry
1
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
tSS
*Note 1
cf.) Once the device enters self refresh mode, minimum t
2
*Note 2
Hi-Z
3
RC
is required after CKE going high to complete self refresh exit.
4
5
6
*Note 3
7
8
- 41
9
10
RAS
Self Refresh Exit
*Note 4
Hi-Z
is required before exit from self refresh.
11
*Note 5
12
13
tRCmin
14
*Note 6
Auto Refresh
15
*Note 7
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
16
17
18
: Don't care
19