km416s1120d ETC-unknow, km416s1120d Datasheet - Page 18

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

KM416S1120D
( Continued )
5. Write Interrupted by Precharge & DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
(b) CL=3, BL=4
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
i) CMD
ii) CMD
iii) CMD
iii) CMD
iv) CMD
interrupt but only the other bank precharge of dual banks operation.
DQM
DQM
DQM
DQM
DQM
DQM
CMD
CLK
CLK
DQ
DQ
DQ
DQ
DQ
DQ
WR
D
0
RD
RD
RD
RD
RD
D
1
WR
D
D
0
2
WR
PRE
D
D
D
1
0
Masked by DQM
3
Note 3
Note 2
WR
Q
Hi-Z
D
D
D
0
0
2
1
Note 1
Hi-Z
WR
D
D
D
D
2
0
3
1
WR
- 18
D
D
D
D
3
2
0
1
D
D
D
3
2
1
D
D
3
2
D
3
CMOS SDRAM
Rev. 1.4 (Jun. 1999)