x40031v14z-bt1 Intersil Corporation, x40031v14z-bt1 Datasheet - Page 5

• Manufacturer Part Number: x40031v14z-bt1
• Description: Triple Voltage Monitor With Integrated Cpu Supervisor
• Manufacturer: Intersil Corporation

A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
*Voltage monitor requires V
PIN CONFIGURATION
PIN DESCRIPTION
Pin
X40030, X40031
X40034, X40035
1
2
3
4
5
6
Device
LOWLINE
-C
-C
-A
-B
-A
-B
V2MON
RESET/
V2FAIL
RESET
Name
MR
NC
LOWLINE
V2MON
RESET
V2FAIL
CC
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V
goes HIGH when V2MON exceeds V
V2 Voltage Monitor Input. When the V2MON input is less than the V
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the V
(X40034, X40035).
Early Low V
when
No connect.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW
whenever V
for the programmed time period (t
released and for t
RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH
whenever V
for the programmed time period (t
released and for t
V
to operate. Others are independent of V
MR
5V; 3V or 3.3V; 1.8V
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
NC
Expected System
SS
3.3V; 2.5V; 1.8V
5V; 3.3V; 1.5V
5V; 3V; 1.8V
14-Pin SOIC, TSSOP
V
Voltages
5
X40030, X40034
1
2
3
4
5
6
7
CC
> V
CC
CC
CC
TRIP1
falls below V
falls below V
Detect. This CMOS output signal goes LOW when
X40030, X40031, X40034, X40035
PURST
PURST
14
13
12
11
10
9
8
.
V
WDO
V3FAIL
V3MON
WP
SCL
SDA
thereafter.
thereafter.
CC
4.55-4.65*
4.35-4.45*
2.95-3.05*
4.55-4.65*
4.55-4.65*
4.55-4.65*
2.0-4.75*
2.0-4.75*
TRIP1
TRIP1
V
CC
(V)
trip1
voltage or if manual reset is asserted. This output stays active
PURST
voltage or if manual reset is asserted. This output stays active
PURST
TRIP2
) on power up. It will also stay active until manual reset is
) on power up. It will also stay active until manual reset is
. There is no power up reset delay circuitry on this pin.
Function
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
LOWLINE
1.70-4.75
2.85-2.95
2.55-2.65
2.15-2.25
0.90-3.50
1.25-1.35
1.25-1.35
0.95-1.05
V2MON
V
V2FAIL
RESET
(V)
trip2
V
MR
NC
SS
14-Pin SOIC, TSSOP
PURST
X40031, X40035
1
2
3
4
5
6
7
thereafter.
1.70-4.75
1.65-1.75
1.65-1.75
1.65-1.75
1.70-4.75
3.05-3.15
2.85-2.95
2.85-2.95
V
V
TRIP2
(V)
trip3
14
13
12
11
10
CC
9
8
< V
voltage, V2FAIL goes
V
WDO
V3FAIL
V3MON
WP
SCL
SDA
CC
TRIP1
RESET = X40030
RESET = X40031
SS
RESET = X40030
RESET = X40031
and goes high
or
(system)
CC
V
TRIP2
POR
CC
input
when
May 25, 2006
and
FN8114.1