x40031v14z-bt1 Intersil Corporation, x40031v14z-bt1 Datasheet - Page 6

• Manufacturer Part Number: x40031v14z-bt1
• Description: Triple Voltage Monitor With Integrated Cpu Supervisor
• Manufacturer: Intersil Corporation

PIN DESCRIPTION
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40030, X40031, X40034,
X40035 activates a Power On Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for t
(X40031, X40035) and RESET (X40030, X40034) pin
allowing the system to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
Pin
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power up.
10
11
12
13
14
7
8
9
PURST
System
Reset
CC
V3MON
V3FAIL
Name
WDO
SDA
(selectable) the circuit releases the RESET
SCL
V
V
WP
exceeds the device V
CC
SS
RESET
X40030/34
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers).
It has an internal pull down resistor. (>10MΩ typical)
V3 Voltage Monitor Input. When the V3MON input is less than the V
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to V
not used. The V3MON comparator is supplied by the V3MON input.
V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V
goes HIGH when V3MON exceeds V
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
Supply Voltage.
(Continued)
MR
6
TRIP1
V
CC
X40030, X40031, X40034, X40035
threshold value
Manual
Reset
TRIP3
. There is no power up reset delay circuitry on this pin.
Function
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t
after.
Low Voltage V
During operation, the X40030, X40031, X40034,
X40035
RESET/RESET if supply voltage falls below a preset
minimum V
microprocessor from operating in a power fail or
brownout
remains active until the voltage drops below 1V. It also
remains active until V
for
Low Voltage V2 Monitoring
The X40030 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
For the X40030 and X40031 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON falling). It also remains active until V2MON
t
PURST
TRIP2
.
monitors
condition.
TRIP1
. The V2FAIL signal is either ORed with
CC
. The RESET signal prevents the
(V1 Monitoring)
the
CC
TRIP3
The
returns and exceeds V
V
CC
voltage, V3FAIL goes
RESET/RESET
level
SS
or
V
and
TRIP3
CC
PURST
when
May 25, 2006
and
asserts
FN8114.1
there-
signal
TRIP1