ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 16

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

8.6
Figure 8-7.
Figure 8-8.
16
Digital Signal Processing
Data_out (DATA)
Data_out (DATA)
Atmel ATA5723C/ATA5724C/ATA5728C
Clock bit-check
counter
Synchronization of the Demodulator Output
Debouncing of the Demodulator Output
Dem_out
Dem_out
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways
and as a result converted into the output signal data. This processing depends on the selected
baud-rate range (BR_Range).
extended clock cycle T
its state only after T
result is always an integral multiple of T
The minimum time period between two edges of the data signal is limited to t
This implies an efficient suppression of spikes at the DATA output. At the same time it limits
the maximum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller.
The maximum time period for DATA to stay low is limited to T
employed to ensure a finite response time in programming or switching off the receiver via pin
DATA. T
ter data stream.
the receiver has switched to receiving mode.
T
t
XClk
DATA_min
DATA_L_max
t
ee
Figure 8-9 on page 17
is therefore longer than the maximum time period indicated by the transmit-
XClk
XClk
has elapsed. The edge-to-edge time period t
. This clock is also used for the bit-check counter. Data can change
t
DATA_min
Figure 8-7
t
ee
XClk
gives an example where Dem_out remains Low after
.
illustrates how Dem_out is synchronized by the
t
ee
t
DATA_min
DATA_L_max
ee
of the Data signal as a
t
ee
. This function is
ee
9248A–RKE–09/11
T
DATA_min
.