ak4420 AKM Semiconductor, Inc., ak4420 Datasheet - Page 13

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ak4420

Manufacturer Part Number
ak4420
Description
192khz 24-bit Stereo ?? Dac With 2vrms Output
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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The AK4420 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4420 is in power-down mode until LRCK are input.
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
MS0683-E-04
supply voltage achieves 80% of VDD. If not, click noise may occur at a different time from this figure.
System Reset
after Time A.
Analog
Circuit
Digital
Circuit
Charge Pump
Circuit
Charge Pump
Counter circuit
MCLK
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8) : Double speed mode
Time A = 1024/ (fs x 4) : Quadruple speed mode
Power Supply
(VDD, CVDD)
D/A In
D/A Out
(Digital)
DZF
(Analog)
Low
Power down
Power down
Power down
“0” data
(6)
Figure 8. System Reset Diagram
20 us
(5)
(1)
(2)
2, 3
LRCK
Power-up
(4)
- 13 -
MUTE (D/A Out)
(3)
Power-up
Power-up
Time A
[AK4420]
2008/06

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