ak4380 AKM Semiconductor, Inc., ak4380 Datasheet - Page 14

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ak4380

Manufacturer Part Number
ak4380
Description
100db 24bit 96khz 2ch Dac
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
n System Reset
The AK4380 should be reset once by bringing PDN = “L” upon power-up. The AK4380 is powered up and the internal
timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The AK4380 is in the power-down
mode until MCLK and LRCK are input.
n Power-down
The AK4380 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
Notes:
MS0018-E-01
(1) The analog output corresponding to the digital input has a group delay, GD.
(2) Analog outputs are floating (Hi-Z) at the power-down mode.
(3) Click noise occures at the edges(“
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is
(6) DZF pin is “L” in the power-down mode (PDN = “L”).
Internal
D/A In
D/A Out
Clock In
MCLK, LRCK, BICK
PDN
External
MUTE
DZF
shown in this figure.
(Digital)
(Analog)
State
(5)
Normal Operation
Figure 6. Power-down/up sequence example
GD
”) of PDN signal. This noise is output even if input data is “0”.
(1)
(3)
(6)
- 14 -
(4)
Mute ON
Power-down
“0” data
Don’t care
(2)
(3)
Normal Operation
GD
(1)
[AK4380]
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