xr16m2752 Exar Corporation, xr16m2752 Datasheet - Page 36

• Manufacturer Part Number: xr16m2752
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16M2752
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
FCTR[2]: IrDa RX Inversion
•
•
FCTR[3]: Auto RS-485 Direction Control
•
•
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
FCTR[6]: Scratchpad Swap
•
•
FCTR[7]: Programmable Trigger Register Select
If using both programmable TX and RX trigger levels, TX trigger levels must be set before RX trigger levels.
•
•
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
4.19
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
Table 10
Enhanced Feature Register (EFR)
for more details.
FCTR
B
IT
0
0
1
1
-5
T
ABLE
FCTR
B
IT
0
1
0
1
-4
14: T
Table
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
RIGGER
15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
36
T
ABLE
T
ABLE
Table 13
S
ELECT
for more details.
REV. 1.0.0