xr16m752im48 Exar Corporation, xr16m752im48 Datasheet
xr16m752im48
Available stocks
Related parts for xr16m752im48
xr16m752im48 Summary of contents
Page 1
MAY 2007 GENERAL DESCRIPTION 1 The XR16M752/XR68M752 (M752 high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The M752 operates from 1.62 to 3.63 volts pin-to-pin and software compatible ...
Page 2
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE IN UT SSIGNMENT RXB 4 RXA 5 XR16M752 6 TXRDYB# 48-pin TQFP TXA 7 Intel Mode Only TXB 8 OP2B# 9 ...
Page 3
... REV. 1.0.2 ORDERING INFORMATION P N ART UMBER XR16M752IL32 32-pin QFN XR16M752IM48 48-Lead TQFP XR68M752IL32 32-pin QFN XR68M752IM48 48-Lead TQFP PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP N AME DATA BUS INTERFACE ...
Page 4
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME INTA (IRQ#) INTB 21 29 (NC) TXRDYA RXRDYA TXRDYB RXRDYB MODEM ...
Page 5
REV. 1.0.2 Pin Description 32-QFN 48-TQFP N AME CTSA DTRA DSRA CDA RIA OP2A TXB 6 8 RXB 3 4 RTSB# 15 ...
Page 6
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME OP2B ANCILLARY SIGNALS XTAL1 10 13 XTAL2 11 14 16/68 RESET 24 36 (RESET#) VCC 26 42 ...
Page 7
REV. 1.0.2 1.0 PRODUCT DESCRIPTION The XR16M752/XR68M752 (M752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is 16550 ...
Page 8
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The XR16M752 data interface ...
Page 9
REV. 1.0.2 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 16). An active high pulse of longer than 40 ns duration will be required ...
Page 10
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.5 DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block transfer operation. The ...
Page 11
REV. 1.0.2 2.7 Crystal Oscillator or External Clock Input The M752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus ...
Page 12
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO When using 4X sampling mode, the bit time will have a jitter of When using a non-standard data rate crystal or external clock, the divisor value can be calculated multiple of 4. with ...
Page 13
REV. 1.0 ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 10000 150 19200 78.125 25000 60 28800 52.0833 38400 39.0625 ...
Page 14
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR ...
Page 15
REV. 1.0.2 2.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It verifies and ...
Page 16
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE ECEIVER PERATION IN 16X Clock ( DLD[5:4] ) Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Data FIFO Receive Data Byte ...
Page 17
REV. 1.0.2 2.14 Auto CTS Flow Control Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected ...
Page 18
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M752 will halt ...
Page 19
REV. 1.0.2 F 11. I IGURE NFRARED 0 TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.18 Sleep Mode with Auto Wake-Up The M752 supports low voltage system designs, hence, a sleep mode is ...
Page 20
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the M752 is in sleep mode, the maximum current will be in the microamp range ...
Page 21
REV. 1.0 IGURE NTERNAL OOP Transmit Shift Register Receive Shift Register HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# ...
Page 22
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M752 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the ...
Page 23
REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDRESS AME RITE A2- RHR RD Bit THR WR Bit IER ...
Page 24
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDRESS AME RITE A2- DLL RD/WR Bit DLM RD/WR Bit-7 ...
Page 25
REV. 1.0.2 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M752 in the FIFO polled mode of operation. Since the receiver and transmitter have ...
Page 26
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# ...
Page 27
REV. 1.0 ABLE P ISR R RIORITY EGISTER EVEL ...
Page 28
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers ...
Page 29
REV. 1.0.2 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the ...
Page 30
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 ...
Page 31
REV. 1.0.2 MCR[2]: OP1# / FIFO Rdy Enable OP1# is not available as an output pin on the M752. But it is available for use during Internal Loopback Mode (MCR[4] = 1). In the Internal Loopback Mode, this bit is ...
Page 32
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit) • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the ...
Page 33
REV. 1.0.2 • Logic global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there ...
Page 34
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.10 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes ...
Page 35
REV. 1.0.2 DLD[ DLD[6]: Auto RS-485 Direction Control • Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register becomes empty and transmit shift register is shifting data out. The RTS# output can ...
Page 36
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ONT EFR[4]: Enhanced Function Bits Enable Enhanced function control ...
Page 37
REV. 1.0.2 • Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH. Data transmission resumes when CTS# returns LOW. 4.14.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are ...
Page 38
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS I/O SIGNALS TX HIGH OP2# HIGH RTS# HIGH DTR# HIGH RXRDY# HIGH TXRDY# LOW INT Three-State Condition 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE ...
Page 39
REV. 1.0.2 DC ELECTRICAL CHARACTERISTICS o o TA= -40 to +85 C, Vcc is 1.62V to 3.63V S P YMBOL ARAMETER V Output High Voltage OH I Input Low Leakage Current IL I Input High Leakage Current IH C Input ...
Page 40
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS o Unless otherwise noted: TA=- YMBOL ARAMETER T Data Hold Time (16 mode Address Setup (68 Mode) ADS T Address Hold (68 Mode) ADH ...
Page 41
REV. 1.0 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI# HIGH PERFORMANCE DUART ...
Page 42
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 15 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ODE NTEL ATA ...
Page 43
REV. 1.0 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# T RDA D0- IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# ...
Page 44
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 19 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX ...
Page 45
REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) F ...
Page 46
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 23 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO ...
Page 47
REV. 1.0.2 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL HIGH PERFORMANCE ...
Page 48
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN ...
Page 49
... Updated pin description table, correct pin # of RXA in QFN-32 package. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
Page 50
XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO GENERAL DESCRIPTION ................................................................................................ 1 A ............................................................................................................................................... 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16M752 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 3 ...
Page 51
REV. 1.0.2 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ FIFO T ABLE RANSMIT AND ECEIVE 4.6 LINE CONTROL REGISTER ...