xr16m752im48 Exar Corporation, xr16m752im48 Datasheet - Page 16

• Manufacturer Part Number: xr16m752im48
• Description: Xr68m752 -high Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see
•
•
If using the Auto RTS interrupt:
•
The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches the Halt Level (TCR[3:0]). The
RTS# pin will return LOW after the RX FIFO is unloaded to the Resume Level (TCR[7:4]). Under these
conditions, the M752 will continue to accept data if the remote UART continues to transmit data. It is the
responsibility of the user to ensure that the Halt Level is greater than the Resume Level. If interrupts are used,
it is recommended that Halt Level > RX Trigger Level > Resume Level. The Auto RTS function is initiated
when the RTS# output pin is asserted LOW (RTS On).
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by DLD
bit-6. It also changes the behavior of the transmit empty interrupt (see
half-duplex direction control signal (RTS#) is LOW for receive mode. When data is loaded into the THR for
transmission, the RTS# output is automatically asserted HIGH prior to sending the data. After the last stop bit
of the last character that has been transmitted, the RTS# signal is automatically de-asserted. This helps in
turning around the transceiver to receive the remote station’s response. When the host is ready to transmit
next polling data packet, it only has to load data bytes to the transmit FIFO. The transmitter automatically re-
asserts RTS# (HIGH) output prior to sending the data.
F
2.11
2.12
2.13
IGURE
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
Receive Data
16X or 8X or 4X Clock
Byte and Errors
64 bytes by 11-bit wide
9. R
Auto RTS (Hardware) Flow Control
Auto RTS Halt and Resume
Auto RS485 Half-duplex Control
( DLD[5:4] )
ECEIVER
FIFO
O
PERATION IN
Receive Data Shift
Register (RSR)
Data FIFO
FIFO
Receive
Receive
Data
AND
A
UTO
Validation
Resume Level
Data falls to
Trigger=16
Data fills to
Data Bit
Halt Level
FIFO
RTS F
Example
16
: - RX FIFO trigger level selected at 16 bytes
LOW
RTS# re-asserts when data falls to the Resume
Enable by EFR bit-6=1, MCR bit-1.
Level to restart remote transmitter.
to suspend remote transmitter.
RTS# de-asserts when data fills to the Halt Level
Enable by EFR bit-6=1, MCR bit-1.
RHR Interrupt (ISR bit-2) programmed for
(See Note Below)
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Figure
C
ONTROL
10):
Table
M
ODE
4). When idle, the auto RS485
Receive Data Characters
RXFIFO1
REV. 1.0.2