sc16c850vibs NXP Semiconductors, sc16c850vibs Datasheet - Page 18
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sc16c850vibs
Manufacturer Part Number
sc16c850vibs
Description
Sc16c850v 1.8 V Single Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And Xscale Vlio Bus Interface
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C850VIBS.pdf
(47 pages)
Table 7.
A3 A2 A1 Register
General Register Set
0
0
0
0
0
0
1
1
1
1
1
Special Register Set
0
0
Second Special Register Set
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
SC16C850V internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
EFCR
MSR
SPR
DLL
DLM
TXLVLCNT
RXLVLCNT
[4]
[2]
[5]
Default
XX
XX
00
00
01
00
00
60
00
X0
FF
XX
XX
00
00
[1]
Bit 7
bit 7
bit 7
CTS
interrupt
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
clock
select
FIFO data
error
reserved
CD
bit 7
bit 7
bit 15
bit 7
bit 7
[3]
[3]
Bit 6
bit 6
bit 6
RTS
interrupt
RCVR
trigger
(LSB)
FIFOs
enabled
set break
IrDA
enable
THR and
TSR empty
reserved
RI
bit 6
bit 6
bit 14
bit 6
bit 6
[3]
Bit 5
bit 5
bit 5
Xoff
interrupt
TX trigger
(MSB)
INT priority
bit 4
set parity
INT type
THR empty break
reserved
DSR
bit 5
bit 5
bit 13
bit 5
bit 5
[3]
[3]
Bit 4
bit 4
bit 4
Sleep
mode
TX trigger
(LSB)
INT priority
bit 3
even parity parity enable
loopback
interrupt
reserved
CTS
bit 4
bit 4
bit 12
bit 4
bit 4
[3]
[3]
Bit 3
bit 3
bit 3
modem status
interrupt
reserved
INT priority
bit 2
OP2
framing error
reserved
bit 3
bit 3
bit 11
bit 3
bit 3
CD
Bit 2
bit 2
bit 2
receive line
status
interrupt
XMIT FIFO
reset
INT priority
bit 1
stop bits
OP1
parity error
Enable extra
feature bit-1
bit 2
bit 2
bit 10
bit 2
bit 2
RI
Bit 1
bit 1
bit 1
transmit
holding
register
interrupt
RCVR FIFO
reset
INT priority
bit 0
word length
bit 1
RTS
overrun error receive data
Enable extra
feature bit-0
bit 1
bit 1
bit 9
bit 1
bit 1
DSR
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT status
word length
bit 0
DTR
ready
Enable
TXLVLCNT/
RXLVLCNT
bit 0
bit 0
bit 8
bit 0
bit 0
CTS
R/W
R
W
R/W
W
R
R/W
R/W
R
W
R
R/W
R/W
R/W
R
R