wm8976gefl-v Wolfson Microelectronics plc, wm8976gefl-v Datasheet - Page 82

• Manufacturer Part Number: wm8976gefl-v
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8976
Figure 46 DAC Power Up and Down Sequence (not to scale)
w
1.
2.
3.
4.
5.
6.
Notes:
The analogue input pin charge time, t
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance
and AVDD power supply rise time.
The analogue input pin discharge time, t
capacitor discharge time. The time, t
input but will vary dependent upon the value of input coupling capacitor.
While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system
noise but no significant digital output will be present.
The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for
normal ADC operation.
ADCDAT data output delay from power –p – with power supplies starting from –V – is
determined primarily by the VMID charge time. ADC initialisation and power management bits
may be set immediately after POR is released; VMID charge time will be significantly longer and
will dictate when the device is stabilised for analogue input.
ADCDAT data output delay at power up from device standby (power supplies already applied) is
determined by ADC initialisation time, 2/fs.
midrail_off
midrail_on,
midrail_off,
, is measured using a 1μF capacitor on the analogue
is determined by the VMID pin charge time. This
is determined by the analogue input coupling
PD Rev 4.4 July 2009
Production Data
82