wm8982gefl-v Wolfson Microelectronics plc, wm8982gefl-v Datasheet - Page 65

• Manufacturer Part Number: wm8982gefl-v
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
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Table 51 Audio Interface Control
ADCLRSWAP bit controls whether the ADC data appears in the right or left phase of the LRC clock
as defined for each audio format. Similarly, DACLRSWAP can be used to swap the left DAC data
from the left phase to the right phase of the LRC clock and the right DAC data from the right phase to
the left phase of the LRC clock.
Note: Right Justified Mode will only operate with a maximum of 24 bits.
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised
below. Each audio interface can be controlled individually.
Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK,
and FRAME are outputs. The frequency of BCLK in master mode are controlled with BCLKDIV.
These are divided down versions of master clock.
R4
Audio
Interface
Control
REGISTER
ADDRESS
0
1
2
4:3
6:5
7
8
BIT
MONO
ADCLRSWAP
DACLRSWAP
FMT
WL
FRAMEP
BCP
LABEL
0
0
0
10
10
DEFAULT
Selects between stereo and mono
device operation:
0=Stereo device operation
1=Mono device operation. Data appears
in ‘left’ phase of FRAME
Controls whether ADC data appears in
‘right’ or ‘left’ phases of FRAME clock:
0=ADC data appear in ‘left’ phase of
FRAME
1=ADC data appears in ‘right’ phase of
FRAME
Controls whether DAC data appears in
‘right’ or ‘left’ phases of FRAME clock:
0=DAC data appear in ‘left’ phase of
FRAME
1=DAC data appears in ‘right’ phase of
FRAME
Audio interface Data Format Select:
00=Right Justified
01=Left Justified
10=I
11= DSP/PCM mode
Word length
00=16 bits
01=20 bits
10=24 bits
11=32 bits (see note)
right, left and i2s modes – FCLK polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
BCLK polarity
0=normal
1=inverted
2
S format
PP, Rev 3.2, September 2008
DESCRIPTION
WM8982
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