wm8982gefl-v Wolfson Microelectronics plc, wm8982gefl-v Datasheet - Page 84

• Manufacturer Part Number: wm8982gefl-v
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

WM8982
REGISTER BITS BY ADDRESS
w
0 (00h)
1 (01h)
2 (02h)
REGISTER
ADDRESS
[8:0]
8
7
6
5
4
3
2
1:0
8
7
6
5
4
3
2
1
BIT
RESET
BUFDCOPEN
OUT4MIXEN
OUT3MIXEN
PLLEN
MICBEN
BIASEN
BUFIOEN
VMIDSEL
ROUT1EN
LOUT1EN
SLEEP
BOOSTENL
INPPGAENL
LABEL
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
N/A
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
DEFAULT
Software reset
Dedicated buffer for DC level shifting output
stages when in 1.5x gain boost configuration.
0=Buffer disabled
1=Buffer enabled (required for 1.5x gain boost)
OUT4 mixer enable
0=disabled
1=enabled
OUT3 mixer enable
0=disabled
1=enabled
PLL enable
0=PLL off
1=PLL on
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Analogue amplifier bias control
0=disabled
1=enabled
Unused input/output tie off buffer enable
0=disabled
1=enabled
Reference string impedance to VMID pin
00=off (open circuit)
01=75kΩ
10=300kΩ
11=5kΩ
ROUT1 output enable
0=disabled
1=enabled
LOUT1 output enable
0=disabled
1=enabled
0 = normal device operation
1 = residual current reduced in device standby
mode
Reserved
Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Reserved
Input PGA enable
0 = disabled
1 = enabled
Reserved
DESCRIPTION
PP, Rev 3.2, September 2008
Resetting the
Chip
Analogue
Outputs
Power
Management
Power
Management
Master Clock
and Phase
Locked Loop
(PLL)
Input Signal
Path
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
REFER TO
Pre-Production
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