wm8903 Wolfson Microelectronics plc, wm8903 Datasheet - Page 37

• Manufacturer Part Number: wm8903
• Description: Ultra Low Power Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
ANALOGUE-TO-DIGITAL CONVERTER (ADC)
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The WM8903 uses two 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback
and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC
full-scale input level is proportional to AVDD. See “Electrical Characteristics” section for further
details. Any input signal greater than full scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits.
Table 8 ADC Enable Control
Configuring the ADC for 96kHz sample rate requires a specific sequence as detailed in the “Clocking
and Sample Rates” section.
ADC DIGITAL VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to
+17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for
a given eight-bit code X is given by:
The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the
ADCL_VOL or ADCR_VOL control data is loaded into the respective control register, but does not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to ADC_VU. This makes it possible to update the gain of both channels simultaneously.
Table 9 ADC Digital Volume Control
R18 (12h)
Power
Management
6
R36 (24h)
ADC Digital
Volume Left
R37 (25h)
ADC Digital
Volume Right
REGISTER
REGISTER
ADDRESS
ADDRESS
MUTE for X = 0
ADC gain = 0.375 × (X-192) dB for 1 ≤ X ≤ 239;
ADC gain = +17.625dB for 239 ≤ X ≤ 255
BIT
BIT
7:0
7:0
1
0
8
8
ADCL_ENA
ADCR_ENA
ADCVU
ADCL_VOL [7:0]
ADCVU
ADCR_VOL [7:0]
LABEL
LABEL
1100_0000
1100_0000
DEFAULT
DEFAULT
(0dB)
(0dB)
N/A
N/A
0
0
Left ADC Enable
0 = disabled
1 = enabled
Right ADC Enable
0 = disabled
1 = enabled
ADC Volume Update
Writing a 1 to this bit causes left
and right ADC volume to be
updated simultaneously
Left ADC Digital Volume
(See Table 10 for volume range)
ADC Volume Update
Writing a 1 to this bit causes left
and right ADC volume to be
updated simultaneously
Right ADC Digital Volume
(See Table 10 for volume range)
PP, Rev 3.1, August 2009
DESCRIPTION
DESCRIPTION
WM8903
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