wm8903 Wolfson Microelectronics plc, wm8903 Datasheet - Page 72

• Manufacturer Part Number: wm8903
• Description: Ultra Low Power Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8903
CHARGE PUMP
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The WM8903 incorporates a dual-mode Charge Pump which generates the supply rails for the
headphone and line output drivers (LINEOUTL/R). The Charge Pump has a single supply input,
CPVDD, and generates split rails VPOS and VNEG according to the selected mode of operation.
The Charge Pump connections are illustrated in Figure 35 (see “Electrical Characteristics” for
external component values). An input decoupling capacitor may also be required at CPVDD,
depending upon the system configuration.
Figure 35 Charge Pump External Connections
The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts
the output voltages (VPOS and VNEG) as well as the switching frequency in order to optimise the
power consumption according to the operating conditions. This can take two forms, which are
selected using the CP_DYN_PWR register bit.
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Under Register control, the HPOUTL_VOL, HPOUTR_VOL, LINEOUTL_VOL and LINEOUTR_VOL
register settings are used to control the charge pump mode of operation.
Under Dynamic control, the audio signal level in the DAC is used to control the charge pump mode of
operation. This is the Wolfson ‘Class W’ mode, which allows the power consumption to be optimised
in real time, but can only be used if the DAC is the only signal source. This mode should not be used
if the Bypass Paths are used to mix additional analogue inputs into the output signal path.
Under the recommended usage conditions of the WM8903, the Charge Pump will be enabled by
running the default Start-Up sequence as described in the “Control Write Sequencer” section.
(Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not
need to write to the CP_ENA bit. The Charge Pump operating mode defaults to Register control;
Dynamic control may be selected by setting the CP_DYN_PWR register bit, if appropriate.
When using the digital sidetone, it is recommended that dynamic control of the charge pump is not
enabled, i.e. CP_DYN_PWR should be cleared to 00. Dynamic control of the charge pump does not
include the sidetone volume in its calculations, hence with a low DAC signal but high sidetone
volume, the headphone amplifier could clip.
CHARGE PUMP CLOCK
The charge pump clock is derived from MCLK, i.e. an MCLK signal must be present for the charge
pump to function. The clock division from MCLK is handled transparently by the WM8903 without
user intervention, as long as MCLK and sample rates are set correctly (see “Clocking and Sample
Rates” section).
The Charge pump is driven from CLK_SYS plus a 4 kHz clock also generated from the CLK_SYS,
and requires a minimum CLK_SYS of 2.8224 MHz. The charge pump internal clock is derived from
CLK_SYS, using a clock divider to generate a nominal 1MHz clock. The clock divider ratio depends
on the SAMPLE_RATE[3:0], CLK_SYS_MODE[1:0], and CLK_SYS_RATE[3:0] register settings.
Register control (CP_DYN_PWR = 0)
Dynamic control (CP_DYN_PWR = 1)
PP, Rev 3.1, August 2009
Pre-Production
72