wm8595 Wolfson Microelectronics plc, wm8595 Datasheet - Page 70

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wm8595

Manufacturer Part Number
wm8595
Description
24-bit 192khz 2vrms Multi-channel Codec
Manufacturer
Wolfson Microelectronics plc
Datasheet

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WM8595
R42 (2Ah) – Audio Interface MUX Configuration Register 3 (AIF_MUX3)
Figure 51 R42 – Audio Interface MUX Configuration Register 3
w
Default
Default
DAC1MCLK_SEL[2:0]
Write
Write
Read
Read
Bit #
Bit #
DAC1DIN_SEL[2:0]
DAC1WORDCLK_
DAC1_UPD
Function
SEL[2:0]
DAC1DIN_
SEL[0]
N/A
15
0
7
0
0
DAC1MCLK Select
000 = Use MCLK1
001 = Use MCLK2
010 to 111 = Reserved
DAC1BCLK and DAC1LRCLK Select
000 = Use BCLK1 and LRCLK1
001 = Use BCLK2 and LRCLK2
010 to 110 = Reserved
111 = Use ADCBCLK and ADCBCLK (when ADC is master mode)
DAC1DIN Select
000 = Use DACDAT1
001 = Use DACDAT2
010 to 100 = Reserved
101 = Use GPIO1
110 = Use GPIO2
111 = Reserved
DAC1 Clock Update
0 = Latch corresponding DAC1 clock settings into Register Map but do not update
1 = Latch corresponding DAC1 clock settings into Register Map and update all simultaneously
N/A
14
0
0
6
0
DAC1WORDCLK_SEL[2:0]
N/A
13
0
0
5
0
N/A
12
0
0
4
0
Description
N/A
11
0
3
0
0
DAC1MCLK_SEL[2:0]
N/A = Not Applicable (no function implemented)
DAC1_UPD
10
0
2
0
DAC1DIN_SEL[2:1]
PD, Rev 4.1, April 2010
9
0
1
0
Production Data
N/A
8
0
0
0
0
70

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