isppac-powr1208p1 Lattice Semiconductor Corp., isppac-powr1208p1 Datasheet - Page 12

• Manufacturer Part Number: isppac-powr1208p1
• Description: In-system Programmable Power Supply Sequencing Controller And Precision Monitor
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 3-2. Comparator Hysteresis vs. Setpoint
The fourth subsystem in the ispPAC-POWR1208P1’s input voltage monitor is a synchronizer latch and optional dig-
ital filter. The synchronizer flip-flop samples the comparator’s output state synchronously with the internal system
clock. Synchronous sampling effectively eliminates the possibility of race conditions occurring in any state-control-
lers implemented in the ispPAC-POWR1208P1’s internal PLD logic.
An optional digital filter is also provided for each comparator input for the purpose of suppressing glitches and other
short transients. This filter is implemented using a saturating counter. When the comparator output is HIGH, the fil-
ter counts up to a maximum of ‘111’, and when the comparator output is LOW the filter counts down to a minimum
of ‘000’. When a ‘111’ count is reached, the output of the filter is set HIGH, and when the ‘000’ count is reached, the
output is set LOW. Because the filter is clocked at the same rate as the synchronizer, the combination of the two
imposes a delay of 8 sampling periods, or 32 clock cycles (32µs at 1MHz). The digital filters may be enabled or dis-
abled individually on a channel-by-channel basis by the user.
PLD Architecture
The ispPAC-POWR1208P1 digital logic is composed of an internal PLD that is programmed to perform the
sequencing functions. The PLD architecture allows flexibility in designing various state machines and control logic
used for monitoring. The macrocell shown in Figure 3-3 is the heart of the PLD. There are 16 macrocells that can
be used to control the functional states of the sequencer state machine or other control or monitoring logic. The
PLD AND array shown in Figure 3-4 has 36 inputs, and 81 product terms (PTs). The resources from the AND array
feed the 16 macrocells. The resources within the macrocells share routing and contain a product-term allocation
array. The product term allocation array greatly expands the PLD’s ability to implement complex logical functions by
allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode
functions.
The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is
independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. Combinatorial functions
are realized by bypassing the flip-flop. By having the polarity control XOR, the logic reduction can be best fit to min-
imize the number of product terms. The flip-flop’s clock is driven from a common clock that can be generated from
a pre-scaled, on-board clock source or from an external clock. The macrocell also supports asynchronous reset
and preset functions, derived from either product terms, the global reset input or the power-on reset signal.
Low Limit
5.017
4.221
3.241
2.724
2.289
1.931
1.618
1.363
1.142
0.962
0.808
0.68
Setpoint Range (V)
80 mV
High Limit
5.932
3.833
3.221
2.706
2.282
1.913
1.137
0.954
0.803
3-12
4.99
1.61
1.35
Hysteresis (mV)
0 (disabled)
ispPAC-POWR1208P1 Data Sheet
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