isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 30

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Table 6. ispPAC20 TAP Instructions
ispPAC20. The bit code of this instruction is defined to be
all ones by the IEEE 1149.1 standard.
The required SAMPLE/PRELOAD instruction dictates the
Boundary-Scan Register be connected between TDI and
TDO. The ispPAC20 has no boundary-scan register, so
for compatibility it defaults to the BYPASS mode when-
ever this instruction is received. The bit code for this
instruction is defined by Lattice as shown in Table 6.
The EXTEST (external test) instruction is required and
would normally place the device into an external bound-
ary test mode while also enabling the Boundary-Scan
Register to be connected between TDI and TDO. Again,
since the ispPAC20 has no boundary-scan logic, the
device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by
the 1149.1 standard to be all zeros.
The optional IDCODE (identification code) instruction is
incorporated in the ispPAC20 and leaves it in its func-
tional mode when executed.
Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register
containing information regarding the IC manufacturer,
device type and version code (see Figure 18). Access to
the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or
by issuing a Test-Logic-Reset instruction. The bit code
for this instruction is defined by Lattice as shown in
Table 6.
EXTEST
ADDUSR
UBE
VERUSR
PRGUSR
IDCODE
ENCAL
DBE
VERDAC
PRGDAC
ADDDAC
SAMPLE
BYPASS
IEEE Standard 1149.1 Interface
Instruction
00000
00001
00010
00011
00100
01101
10000
10001
10010
10011
10100
11110
11111
Code
External test. Default to BYPASS.
Address user data register.
User bulk erase.
Verify user data register.
Program user data register.
Read identification data register.
Enable calibration sequence.
DAC bulk erase.
Verify the DAC register.
Program the DAC register.
Address the DAC register.
Sample/Preload. Default to BYPASS.
Bypass (connect TDI to TDO).
Description
It selects the Device
TAP Inst/PAC20
30
Figure 18. Identification Code (IDCODE) 32-Bit
Binary Word for Lattice ispPAC20
ADDUSR (address user register) instruction is a Lattice
defined instruction that selects the user register to be
shifted during a Shift-DR operation. Normal operation of
a device is not interrupted by this instruction. It precedes
a PROGUSR (program user) instruction to shift in a new
configuration and follows a VERUSR (verify user) in-
struction to shift out the current configuration. The bit
code for this instruction is shown in Table 6.
The PRGUSR (program user) is a Lattice instruction that
enables the data shifted into the user register to be
programmed into the non-volatile E
the ispPAC20 and thereby alter its configuration. The
user register is a 109-bit shift register that contains all the
user-controlled parametric and interconnect data per-
taining to the configuration of the ispPAC20. Normal
operation of the device is interrupted during the actual
programming time. A programming operation does not
begin until entry of the Run-Test/Idle state. The time
required to insure data retention is given in the TAP signal
specifications table. The user must ensure that the rec-
ommended programming times are observed. The bit
code for this instruction is shown in Table 6.
VERUSR (verify user) is the next Lattice instruction and
causes the current configuration of the ispPAC20 to be
loaded into the user register. This operation doesn’t
interrupt operation of the device. The current configura-
tion can then be shifted out of the user register immediately
after an ADDUSR instruction is executed. The bit code for
this instruction is shown in Table 6.
For DAC operations, the ADDDAC (address DAC),
PRGDAC (program DAC), VERDAC (verify DAC) and
DBE (DAC bulk erase, instructions are provided. They
have basically the same effect as the “user” instructions
MSB
E 2 Configured
XXXX / 0000 0001 0001 0001 / 0000 0100 001 / 1
Version
(4 bits)
Specifications ispPAC20
0111h = PAC20
Part Number
(16 bits)
Lattice Semiconductor
JEDEC Manfacturer
Identity Code for
(11 bits)
2
CMOS memory of
per 1149.1-1990
Constant 1
(1 bit)
LSB