isppac-powr1014 Lattice Semiconductor Corp., isppac-powr1014 Datasheet
isppac-powr1014
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isppac-powr1014 Summary of contents
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... POL#N ADC* 4 Timers ispPAC-POWR1014A *ispPAC-POWR1014A only. Description Lattice’s Power Manager II ispPAC-POWR1014 general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor power supply test points ...
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... MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD ...
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... OUT13 Open Drain Output 1 OUT14 Open Drain Output 8 40 RESETb Digital I/O 42 PLDCLK Digital Output ispPAC-POWR1014/A Data Sheet Voltage Range 1 VCCINP PLD Logic Input 1 Registered by MCLK 1 VCCINP PLD Logic Input 2 Registered by MCLK 1 VCCINP PLD Logic Input 3 Registered by MCLK 1 VCCINP PLD Logic Input 4 Registered by MCLK 4 -0 ...
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... GNDA and GNDD pins must be connected together on the circuit board. 6. VCCD and VCCA pins must be connected together on the circuit board. 7. Open-drain outputs require an external pull-up resistor to a supply. 8. The RESETb pin should only be used for cascading two or more ispPAC-POWR1014/A devices. 9. These pins should be connected to GNDD (ispPAC-POWR1014 device only). Voltage Range ...
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... Supply current CCPROG 1. Includes currents on V and V CCD CCA Parameter Conditions HVOUT[1:2] OUT[3:14] Conditions 2 During E programming pins MON OUT[3:14] pins HVOUT[1:2] pins in open- drain mode Power applied Conditions During programming cycle supplies. 2-5 ispPAC-POWR1014/A Data Sheet Min. Max. -0.5 4.5 -0.5 4.5 -0.5 6 -0.5 6 -0.5 4 -0.5 6 -0.5 6 -0 -65 150 ...
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... Gate driver sink current I OUTSINK (LOW state) Conditions 1 range, operating temperature, process. CCA Conditions 10V setting 8V setting 6V setting Four settings in software FAST OFF mode Controlled ramp settings 2-6 ispPAC-POWR1014/A Data Sheet Min. Typ. Max 0.075 5.867 0.3 0.9 1 Min. ...
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... Corresponds to VCCA and VCCD supply voltages. Conditions 2 Time from I C request Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 1 Programmable attenuator = 3 Programmable attenuator = 3 pin (theoretical maximum is 6.144V). Conditions Measurement Range 600 mV - 2.048V, Attenuator =1 Conditions 2-7 ispPAC-POWR1014/A Data Sheet Min. Typ. Max. 10 100 0 2.048 +/- 0.1 1 Min. Typ. Max. -8 ...
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... Lattice Semiconductor Figure 2-2. ispPAC-POWR1014/A Power-On Reset Reset State T BRO T T RST POR Start Up State T START Analog Calibration T GOOD 2-8 ispPAC-POWR1014/A Data Sheet VCC RESETb MCLK PLDCLK AGOOD (Internal) ...
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... Range of programmable Timeout Range timers (128 steps) Spacing between available Resolution adjacent timer intervals Accuracy Timer accuracy Over Recommended Operating Conditions Conditions f = 8MHz CLK f = 8MHz CLK f = 8MHz CLK 2-9 ispPAC-POWR1014/A Data Sheet Min. Typ. Max 7.6 8 8.4 7.2 8.8 250 0.032 1966 13 -6.67 -12.5 Units µs µs ...
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... SCL, SDA IN[1:4] TDI, TMS, ATDI, TDISEL, 3.3V supply TDI, TMS, ATDI, 1 TDISEL, 2.5V supply SCL, SDA IN[1: 10mA SINK I = 20mA SINK I = 4mA SINK I = 4mA SRC CCJ 2-10 ispPAC-POWR1014/A Data Sheet Min. Typ. Max. +/- 0.8 0.7 30% V CCD 30% V CCINP 2.0 1.7 70 CCD CCD 70 CCINP CCINP ...
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... Device must be operational after power-on reset POR T Bus free time between stop and start condition BUF 1. Applies to ispPAC-POWR1014A only less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this ...
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... SU1 CKH Select-DR Scan SU1 H SU1 CKL PWP CKH Run-Test/Idle (Program) Select-DR Scan 2-12 ispPAC-POWR1014/A Data Sheet Min. Typ. Max. 10 — — 30 — — 30 — — 200 — — — — 10 — — — — ...
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... Theory of Operation Analog Monitor Inputs The ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in Figure 2-7. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a 75mV ‘ ...
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... Lattice Semiconductor Figure 2-7. ispPAC-POWR1014/A Voltage Monitors VMONx Trip Point A Trip Point B Analog Input Figure 2-7 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. ...
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... To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. UTP LTP 2-15 ispPAC-POWR1014/A Data Sheet (a) (b) ...
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... Data Sheet 2.719 3.223 3.839 4.926 2.705 3.206 3.819 4.900 2.691 3.190 3.799 4.875 2.677 3.173 3.779 4.849 2 ...
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... Data Sheet 2.691 3.190 3.799 4.875 2.677 3.173 3.779 4.849 2.663 3.156 3.759 4.823 2.649 3.139 3.739 4.798 2.634 3 ...
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... The third section in the ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the compara- tor output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the fi ...
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... Lattice Semiconductor VMON Voltage Measurement with the On-chip Analog to Digital Converter (ADC, ispPAC- POWR1014A Only) The ispPAC-POWR1014A has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. Figure 2-9. ADC Monitoring VMON1 to VMON10 VMON1 VMON2 VMON3 Programmable Analog ...
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... GLB1, GLB2, and GLB3. Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the ispPAC-POWR1014/A device. The output signals of the ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 2-10. GLB3 gen- erates timer control ...
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... PT0 Polarity Clock Clock and Timer Functions Figure 2-12 shows a block diagram of the ispPAC-POWR1014/A’s internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 2-12. Clock and Timer System Internal Oscillator 8MHz The internal oscillator runs at a fi ...
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... In addition to being usable as digital open-drain outputs, the ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output pins can be programmed to operate as high-voltage FET drivers. Figure 2-14 shows the details of the HVOUT gate drivers. Each of these outputs may be controlled from the PLD, or with the ispPAC-POWR1014A, from the I (see Figure 2-14). For further details on controlling the outputs through I section of this data sheet ...
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... CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPAC- POWR1014/A device operation, results in the device aborting all operations and returning to the power-on reset state. The status of the power supplies which are being enabled by the ispPAC-POWR1014/A will be determined by the state of the outputs shown above. ...
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... Each slave device on a given I C bus is assigned a unique address. The ispPAC-POWR1014A implements the 7-bit addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR1014A device by pro- gramming through JTAG. When selecting a device address, one should note that several addresses are reserved ...
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... START DEVICE ADDRESS (7 BITS) Reading a data byte from the ispPAC-POWR1014A requires two separate bus transactions (Figure 2-17). The first transaction writes the register address from which a data byte read. Note that since no data is being written to the device, the transaction is concluded after the second byte frame. The second transaction performs the actual read. The fi ...
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... C interface to the ADC (Figure 2-19). 2-26 ispPAC-POWR1014/A Data Sheet Value After POR – – – – – – – – – – – – – – – – – – – – – – – – – – – – ...
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... Select Word SEL2 SEL1 (ADC_MUX.2) (ADC_MUX. 2-27 ispPAC-POWR1014/A Data Sheet 1 1 DONE SEL2 SEL1 SEL0 Full-Scale Range 2.048 V 6.144 V SEL0 (ADC_MUX.0) Input Channel 0 VMON1 1 VMON2 0 ...
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... MUX 3 3 Input_Value Input_Status Interface Unit IN4 2-28 ispPAC-POWR1014/A Data Sheet more than 50kHz and verify 2 C commands. Figure 2-20 PLD Array IN3 IN2 IN1 interface, as shown in Figure 2-21. The 2 C ...
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... OUT12 GP6 GP5 GP4 GP14 GP13 GP12 interface, with the register mapping shown in Figure 2-22. 2-29 ispPAC-POWR1014/A Data Sheet C bus instead of by the PLD array. The outputs 14 HVOUT[1..2] OUT[3..14] OUT3 HVOUT2 HVOUT1 OUT11 OUT10 OUT9 GP3_ENb GP2 ...
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... The I C interface also provides the ability to initiate reset operations. The ispPAC-POWR1014A may be reset by issuing a write of any value to the I is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I section of this data sheet for further information. ...
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... After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ispPAC-POWR1014A. As part of the service functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP3_ENb to re-enable the SMBAlert function ...
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... To meet such application needs, the ispPAC-POWR1014/A provides an alternate programming method which enables the programming of the ispPAC-POWR1014/A device through the JTAG chain with a sepa- rate power supply applied just to the programming section of the ispPAC-POWR1014/A device with the main power supply of the board turned off. ...
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... TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the ispPAC-POWR1014/A are connected to the header as shown in Figure 2-27. Note: The ispPAC-POWR1014/A should be the last device in the JTAG chain. ...
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... VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the ispPAC-POWR1014/A is using the VCCPROG pin, its VCCD and VCCA pins can be open or pulled low. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOSFET driver are driven low, and all other inputs are ignored ...
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... IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispPAC-POWR1014/A is facilitated via an IEEE 1149.1 test access port (TAP used by the ispPAC-POWR1014 serial programming interface. A brief descrip- tion of the ispPAC-POWR1014/A JTAG interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149 ...
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... E CMOS cells these non-volatile cells that store the configuration or the ispPAC-POWR1014/A. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibil- ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func- tionally specifi ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver- ...
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... POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 2-11 ...
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... Lattice Semiconductor ispPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000). The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR1014/A and leaves it in its functional mode when executed. It selects the Device Identifi ...
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... Lattice Semiconductor DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispPAC-POWR1014/A for a read cycle. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_ADDRESS – This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_DATA_SHIFT – ...
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... The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. ERASE_DONE_BIT – This instruction clears the 'Done' bit, which prevents the ispPAC-POWR1014/A sequence from starting. PROGRAM_DONE_BIT – This instruction sets the 'Done' bit, which enables the ispPAC-POWR1014/A sequence to start. RESET – ...
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... A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. 0. SEATING PLANE 0.08 C LEAD FINISH BASE METAL 2-42 ispPAC-POWR1014/A Data Sheet 0. 0.20 MIN. A1 1.00 REF. DETAIL "A" SYMBOL MIN ...
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... Lattice Semiconductor Part Number Description ispPAC-POWR1014X - 01XX48X Device Family Device Number ADC Support A = ADC present ispPAC-POWR1014/A Ordering Information Conventional Packaging Part Number ispPAC-POWR1014A-01T48I ispPAC-POWR1014-01T48I Lead-Free Packaging Part Number ispPAC-POWR1014A-01TN48I ispPAC-POWR1014-01TN48I ispPAC-POWR1014/A Data Sheet Operating Temperature Range I = Industrial (-40 Package T = 48-pin TQFP TN = Lead-Free 48-pin TQFP* ...
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... Lattice Semiconductor Package Options OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 ispPAC-POWR1014A 6 48-Pin TQFP 2-44 ispPAC-POWR1014/A Data Sheet 36 VMON9 35 VMON8 34 VMON7 33 VMON6 32 VMON5 31 GNDD 30 GNDA 29 VCCA 28 VMON4 27 VMON3 26 VMON2 25 VMON1 ...
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... Lattice Semiconductor Package Options (Cont.) OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 GNDD OUT8 OUT7 OUT6 OUT5 OUT4 ispPAC-POWR1014/A Data Sheet ispPAC-POWR1014 6 48-Pin TQFP 2-45 36 VMON9 35 VMON8 34 VMON7 33 VMON6 32 VMON5 31 GNDD 30 GNDA 29 VCCA 28 VMON4 27 VMON3 26 VMON2 25 VMON1 ...
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... Added timing diagram and timing parameters to "Power-On Reset" specifications. Modified PLD Architecture figure to show input registers. 2 Updated I C Control Registers table. V pin usage clarification added. CCPROG 2-46 ispPAC-POWR1014/A Data Sheet “SELTDI” changed to “TDISEL” frequency and V specifications for I C interface ...