isppac-powr1014 Lattice Semiconductor Corp., isppac-powr1014 Datasheet - Page 23

• Manufacturer Part Number: isppac-powr1014
• Description: In-system Programmable Power Supply Supervisor, Reset Generator And Sequencing Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Figure 2-14 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources
current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also
programmable between 6V and 10V. The maximum voltage levels that are required depend on the gate-to-source
threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs
to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET’s
source, since the source pin of the FET to provide a wide range of ramp rates is tied to the supply of the target
board. When the HVOUT pin is sourcing current, charging a FET gate, the source current is programmable
between 12.5µA and 100µA. When the driver is turned to the off state, the driver will sink current to ground, and
this sink current is also programmable between 3000µA and 100µA to control the turn-off rate.
Programmable Output Voltage Levels for HVOUT1- HVOUT2
There are three selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage
that the pin is capable of driving to can be programmed from 6V to 10V in 2V steps.
RESETb Signal, RESET Command via JTAG or I
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG, or with
the ispPAC-POWR1014A, I
been configured in the PINS window:
At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMONs, and ADCs will not be operational until 500 microseconds (max.) after the
conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPAC-
POWR1014/A device operation, results in the device aborting all operations and returning to the power-on reset
state. The status of the power supplies which are being enabled by the ispPAC-POWR1014/A will be determined by
the state of the outputs shown above.
I
I
devices on a circuit board. The ispPAC-POWR1014A supports a 7-bit addressing of the I
2
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
C/SMBUS Interface (ispPAC-POWR1014A Only)
• OUT3-14 will go high-impedance.
• HVOUT pins programmed for open drain operation will go high-impedance.
• HVOUT pins programmed for FET driver mode operation will pull down.
Digital Control from I
(ispPAC-POWR1014A Only)
Digital Control
2
C will force the outputs to the following states independent of how these outputs have
from PLD
Charge Pump
(6 to 10V)
2
C Register
+
-
(100 to 500 µA)
+Fast Turn-off
(3000µA)
I
SINK
2-23
2
(12.5 to 100 µA)
C
I
SOURCE
ispPAC-POWR1014/A Data Sheet
HVOUTx
Pin
Supply
Input
Load
2
C communications proto-