isppac10 Lattice Semiconductor Corp., isppac10 Datasheet
isppac10
Manufacturer Part Number
isppac10
Description
In-system Programmable Analog Circuit
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.ISPPAC10.pdf
(48 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
isppac10-01SI
Manufacturer:
LATTICE
Quantity:
20 000
December 2001
Features
Table 1. ispMACH 5000VG Family Selection Guide
www.latticesemi.com
Macrocells
User I/O Options
t
t
t
f
Supply Voltage (V)
Package
PD
S
CO
MAX
– Set-up with 0 Hold (ns)
High Density
sysCLOCK™ PLL – Timing Control
High Speed Logic Implementation
sysIO™ Capability
(ns)
(ns)
(MHz)
• 768 to 1,024 macrocells
• 196 to 384 I/Os
• Multiply and divide factors between 1 and 32
• Clock shifting capability ± 3.5ns in 500ps steps
• Multiple output frequencies
• External feedback capability for board-level
• LVDS/LVPECL clock input capability
• SuperWIDE 68-input logic block
• Up to 160 product terms per output
• Hierarchical routing structure provides fast inter-
• LVCMOS 1.8, 2.5 and 3.3
• LVTTL
• SSTL 2 (I & II)
• SSTL 3 (I & II)
• CTT 3.3, CTT 2.5
• HSTL (I & III)
• PCI-X, PCI 3.3
• GTL+
• AGP-1X
• 5V tolerance
• Programmable drive strength
clock deskew
connect
ispMACH 5000VG Family
256-ball fpBGA
484-ball fpBGA
ispMACH
5768VG
196/304
3.3V
768
178
5.0
3.0
4.4
1
ispMACH 5000VG Introduction
The ispMACH 5000VG represents the third generation
of Lattice’s SuperWIDE CPLD architecture. Through
their wide 68-input blocks, these devices give signifi-
cantly improved speed performance for typical designs
over architectures with fewer inputs.
The ispMACH 5000VG takes the unique benefits of the
SuperWIDE architecture and extends it to higher densi-
ties referred to as SuperBIG, by using the combination
of an innovative product term architecture and a two-
tiered hierarchical routing architecture. Additionally,
sysCLOCK and sysIO capabilities have been added to
maximize system-level performance and integration.
SuperBIG, SuperWIDE High Density PLDs
Ease of Design
Easy System Integration
• Product term sharing
• Extensive clocking and OE capability
• 3.3V power supply
• Hot socketing
• Input pull-up, pull-down or bus-keeper
• Open drain capability
• Slew rate control
• Macrocell-based power management
• IEEE 1149.1 boundary scan testable
• In-system programmable via IEEE 1532 ISC
compliant interface
TM
TM
3.3V In-System Programmable
484-ball fpBGA
676-ball fpBGA
TM
ispMACH
51024VG
304/384
1,024
3.3V
178
5.0
3.0
4.4
Data Sheet
5kvg_09
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