net2890 ETC-unknow, net2890 Datasheet - Page 25

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
4.5.4 Bulk Endpoints
Bulk endpoints are used for guaranteed error-free delivery of large amounts of data between a host and
device. Bulk endpoints are unidirectional, with the direction defined by the endpoint configuration registers.
4.5.4.1 Bulk Out Transactions
Bulk Out endpoints are used to transfer data from a USB host to the NET2890 local bus. A bulk write
transaction to a Bulk Out endpoint consists of the following:
The USB host initiates a Bulk OUT transaction by sending an OUT token to a Bulk OUT endpoint. The
Data OUT Token Interrupt status bit is set when the OUT token is recognized. If this interrupt is
enabled, the local interrupt IRQ# pin is asserted. The bytes corresponding to the Data stage are stored into
the endpoint’s FIFO. If the FIFO is full when another byte is transferred from the host, the byte will be
discarded and the USB OUT NAK Sent status bit will be set. At the completion of the packet, a NAK
handshake will be returned to the host, indicating that the packet could not be accepted.
All USB data passes through the endpoint’s FIFO to the local bus. The local CPU can poll the FIFO
Empty status bit or the FIFOCNT register to determine when valid data is available. Also, the endpoint
FIFO Almost Full Threshold Register can be programmed to generate an interrupt when a selected
number of bytes have been received. If the local CPU knows that an incoming packet will fit entirely into
the FIFO, it can wait until Data Packet Received Interrupt occurs before reading the data from the FIFO.
The local CPU can use the following methods to read the OUT data from the endpoint’s FIFO:
After each transaction, the local CPU should check the USB OUT ACK Sent, USB OUT NAK Sent, and
Timeout status bits to determine if the packet was successfully received.
____________________________________________________________________________________
Poll the FIFO Empty status bit to determine when a valid data is available.
Poll the Data Packet Received Interrupt status bit, or enable it to generate a local interrupt. The
Maximum Packet Size must be less than the FIFO size.
Poll the FIFO Almost Full Interrupt status bit, or enable it to generate a local interrupt.
If a packet is not successfully received (USB OUT NAK Sent or Timeout status bits set) and retries
are disabled, the Data Packet Received Interrupt status bit will be set. The packet data which is in
the FIFO or has already been read by the CPU should be discarded. The host will resend the same
packet again.
If a packet is not successfully received (USB OUT NAK Sent or Timeout status bits set) and retries
are enabled, the Data Packet Received Interrupt status bit will not be set, and the data will be
automatically flushed from the FIFO. The host will resend the same packet again. This process is
transparent to the local CPU.
If the local CPU has stalled this endpoint by setting the Endpoint Stall bit, the NET2890 will not store
any data into the FIFO, and will respond with a STALL acknowledge to the host.
Stage
OUT Token
Data (1/0)
Status
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
Packet Contents
OUT PID, address, endpoint, and CRC5
DATA PID, N data bytes, and CRC16
ACK, NAK, or STALL
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
bytes
N+3
# of
3
1
NET2890
Source
Host
Host
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