net2890 ETC-unknow, net2890 Datasheet - Page 45

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
5.4.4 (Address 13h; EPIRQENB) Endpoint Interrupt Enable Register (one per
Endpoint)
5.4.5 (Address 14h; EPIRQSTAT) Endpoint Interrupt Status Register (one per
Endpoint)
Bits
Bits
____________________________________________________________________________________
7:6
7:6
5
4
3
2
1
0
5
4
3
2
1
0
Description
Reserved.
Data Packet Received Interrupt Enable. When set, this bit enables a local interrupt
to be set when a data packet has been received from the host.
Data Packet Transmitted Interrupt Enable. When set, this bit enables a local
interrupt to be set when a data packet has been transmitted to the host.
Data OUT Token Interrupt Enable. When set, this bit enables a local interrupt to
be set when a Data OUT token has been received from the host.
Data IN Token Interrupt Enable. When set, this bit enables a local interrupt to be
set when a Data IN token has been received from the host.
FIFO Almost Full Interrupt Enable. When set, this bit enables a local interrupt to
be set when the number of bytes in the FIFO becomes equal to or greater than the
FIFO Almost Full Threshold.
FIFO Almost Empty Interrupt Enable. When set, this bit enables a local interrupt
to be set when the number of bytes in the FIFO becomes equal to or less than the
FIFO Almost Empty Threshold.
Description
Reserved.
Data Packet Received Interrupt. This bit is set when a data packet is received from
the host by this endpoint. This status bit is cleared by writing a 1. If this bit is set,
the Receive Handshake Mode bit is set, and another OUT token is received, a NAK
is returned to the host.
Data Packet Transmitted Interrupt. This bit is set when a data packet is
transmitted from the endpoint to the host. This status bit is cleared by writing a 1.
Data OUT Token Interrupt. This bit is set when a Data OUT token has been
received from the host. This status bit is cleared by writing a 1.
Data IN Token Interrupt. This bit is set when a Data IN token has been received
from the host. This status bit is cleared by writing a 1.
FIFO Almost Full Interrupt. This bit is set when the number of bytes in the FIFO
changes from a value less than the FIFO Almost Full Threshold to a value equal to or
greater than the threshold.
FIFO Almost Empty Interrupt. This bit is set when the number of bytes in the
FIFO changes from a value greater than the FIFO Almost Empty Threshold to a
value equal to or less than the threshold.
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Write
Write
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Default
Default
Value
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
45