net2890 ETC-unknow, net2890 Datasheet - Page 40

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
5.3.4 (Address 03h; IRQSTAT1) Interrupt Status Register 1
5.3.5 (Address 04h; IRQSTAT2) Interrupt Status Register 2
NOTE: These status bits are set independently of the corresponding interrupt enable bits. Writing a 0 to
these bits has no effect.
Bits
Bits
____________________________________________________________________________________
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Description
SOF Interrupt Status. This bit indicates when a start-of-frame packet has been
received by the NET2890. This status bit is cleared by writing a 1.
Reserved.
Interrupt Status 2. This bit indicates when one of the IRQSTAT2 interrupt bits is
active and the corresponding interrupt is enabled. Note that this bit is not set as a
result of “Suspend Control” being active.
Endpoint D Interrupt Status. This bit conveys the interrupt status for Endpoint D.
If set, Endpoint D’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Endpoint C Interrupt Status. This bit conveys the interrupt status for Endpoint C.
If set, Endpoint C’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Endpoint B Interrupt Status. This bit conveys the interrupt status for Endpoint B.
If set, Endpoint B’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Endpoint A Interrupt Status. This bit conveys the interrupt status for Endpoint A.
If set, Endpoint A’s interrupt status register should be read to determine the cause of
the interrupt. This bit is set independently of the interrupt enable bit.
Endpoint 0 Interrupt Status. This bit conveys the interrupt status for Endpoint 0. If
set, Endpoint 0’s interrupt status register should be read to determine the cause of the
interrupt. This bit is set independently of the interrupt enable bit.
Description
Control Status Interrupt. This bit is set when an IN or OUT token indicating
Control Status has been received. This status bit is cleared by writing a 1.
Setup Packet Interrupt. This bit is set when a setup packet has been received from
the host. This bit must be cleared (by writing a 1) before the next setup packet can be
received. If the bit is not cleared, successive setup packets will not be acknowledged.
Input Pin Change Interrupt Status. If set, this bit indicates that a change occurred
in the BUSPWR# or PWRGOOD# input pins. Read the MAINCTL register for the
current state of these pins. This status bit is cleared by writing a 1.
Suspend Control. If set, this bit indicates that there is a pending suspend request
from the host. Writing a 1 clears this bit and causes the NET2890 to enter the
suspended state.
EOT Interrupt Status. This bit indicates when the EOT# input has been asserted
simultaneously with DACK# and either IOR# or IOW#, indicating the completion of
a DMA transfer. This status bit is cleared by writing a 1. This bit is set independently
of the corresponding interrupt enable bit.
Root Port Reset Interrupt Status. This bit indicates when a root port reset has been
received by the NET2890. This status bit is cleared by writing a 1.
Suspend Request Interrupt Status. This bit indicates when a suspend-request has
been received by the NET2890. This status bit is cleared by writing a 1.
Resume Interrupt Status. If set, this bit indicates that a device resume has occurred.
This status bit is cleared by writing a 1.
335 Pioneer Way, Mountain View, California 94041
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NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Yes/CLR
Write
Write
No
No
No
No
No
No
No
Default
Default
Value
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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