net2890 ETC-unknow, net2890 Datasheet - Page 47

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
5.4.9 (Address 1Ah; FIFOCNT) FIFO Count Register (one per Endpoint)
5.4.10 (Address 1Ch;FIFOCTL) FIFO Control Register (one per Endpoint)
5.4.11 (Address 1Eh;FIFOSTAT) FIFO Status Register (one per Endpoint)
Bits
Bits
Bits
____________________________________________________________________________________
7:0
4:0
1:0
7
6
5
7
6
5
4
3
2
Description
FIFO Count. This register returns the number of FIFO entries containing valid data.
Values range from 0 (empty) to 128 (full) for Endpoints A through D, and from 0
(empty) to 16 (full) for Endpoint 0. Note: If retries are disabled, and the endpoint is
actively involved in a USB packet transfer, the value read from this register may not
be valid.
Description
Reserved
FIFO Valid Mode.
This bit is only used for IN endpoints. Setting this bit causes the NET2890 to
respond to an IN token with a NAK handshake unless there are more than
EPnPKTSIZ bytes in the FIFO or the FIFO Valid bit is set. When this bit is cleared,
any data waiting in the endpoint’s FIFO will be sent in response to a
n IN token, and the FIFO Valid bit is ignored (except for zero-length packets).
FIFO Flush. Writing a 1 to this bit causes the FIFO to be flushed and the
corresponding FIFO Count register and FIFO Valid bit to be cleared. This bit clears
itself, and writing a 0 has no effect. Reading this bit always returns a 0.
Reserved
Description
FIFO Valid.
This bit is only used for IN endpoints. If the FIFO Valid Mode bit is set and there are
fewer than EPnPKTSIZ bytes in the FIFO, the NET2890 will respond to IN tokens
with NAK handshake unless this bit is set. Setting this bit causes the data in the FIFO
to be returned to the host as a short packet. Setting this bit when the FIFO is empty
causes a zero-length packet to be returned. This bit is automatically cleared when a
short (fewer than EPnPKTSIZ) packet is transmitted to the Host PC. (See
EPnPKTSIZ registers).
Reserved
FIFO Overflow. If set, this bit indicates that an attempt was made to write to the
FIFO when the FIFO was full. Writing a 1 clears this bit.
FIFO Underflow. If set, this bit indicates that an attempt was made to read the FIFO
when the FIFO was empty. Writing a 1 clears this bit.
FIFO Full. If set, this bit indicates that the FIFO is full.
FIFO Empty. If set, this bit indicates that the FIFO is empty.
Reserved
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
Read
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes/CLR
Yes/CLR
Yes/SET
Write
Write
Write
Yes
Yes
No
No
No
No
No
No
No
Default
Default
Default
Value
Value
Value
0
0
0
0
0
0
0
0
0
0
1
0
47