ox16pci954 ETC-unknow, ox16pci954 Datasheet - Page 14

• Manufacturer Part Number: ox16pci954
• Description: Integrated Quad Uart Interface
• Manufacturer: ETC-unknow

6
6.1
The OX16PCI954 responds to the following PCI
transactions:-
The OX16PCI954 will complete all transactions as
disconnect-with-data, ie the device will assert the STOP#
signal alongside TRDY#, to ensure that the Bus Master
does not continue with a burst access. The exception to
this is Retry, which will be signalled in response to any
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
Configuration access: The OX16PCI954 responds to
type 0 configuration reads and writes if the IDSEL
signal is asserted and the bus address is selecting the
configuration registers for function 0 or 1. The device
will respond to the configuration transaction by
asserting DEVSEL#. Data transfer then follows. Any
other configuration transaction will be ignored by the
OX16PCI954.
IO reads/writes: The address is compared with the
addresses reserved in the I/O Base Address Registers
(BARs). If the address falls within one of the assigned
ranges, the device will respond to the IO transaction
by asserting DEVSEL#. Data transfer follows this
address phase. For the UARTs and 8-bit Local Bus
controller, only byte accesses are possible. For IO
accesses to these regions, the controller compares
AD[1:0] with the byte-enable signals as defined in the
PCI specification. The access is always completed;
however if the correct BE signal is not present the
transaction will have no effect
Memory reads/writes: These are treated in the same
way as I/O transactions, except that the memory
ranges are used. Memory access to single-byte
regions is always expanded to DWORDs in the
OX16PCI954. In other words, OX16PCI954 reserves
a DWORD per byte in single-byte regions. The device
allows the user to define the active byte lane using
LCC[4:3] so that in Big-Endian systems the hardware
can swap the byte lane automatically. For Memory
mapped
OX16PCI954 compares the asserted byte-enable with
the selected byte-lane in LCC[4:3] and completes the
operation if a match occurs, otherwise the access will
complete normally on the PCI bus, but it will have no
effect on either the internal UARTs or the local bus
controller.
All other cycles (64-bit, special cycles, reserved
encoding etc.) are ignored.
PCI T
Operation
ARGET
access
C
ONTROLLER
in
single-byte
regions,
the
access while the OX16PCI954 is reading from the serial
EEPROM.
The OX16PCI954 performs medium-speed address
decoding as defined by the PCI specification. It asserts the
DEVSEL# bus signal two clocks after FRAME# is first
sampled low on all bus transaction frames which address
the chip. The internal UARTs are accessed with zero wait
states inserted. Fast back-to-back transactions are
supported by the OX16PCI954 as a target, so a bus master
can perform faster sequences of write transactions to the
UARTs or local bus when an inter-frame turn-around cycle
is not required.
The device supports any combination of byte-enables to
the PCI Configuration Registers, the Local Configuration
registers (see Base Address 2 and 3) and the Local Bus
controller in 32-bit mode. If a byte-enable is not asserted,
that byte is unaffected by a write operation and undefined
data is returned upon a read.
The OX16PCI954 performs parity generation and checking
on all PCI bus transactions as defined by the standard.
Note this is entirely unrelated to serial data parity which is
handled within the UART functional modules themselves. If
a parity error occurs during the PCI bus address phase, the
device will report the error in the standard way by asserting
the SERR# bus signal. However if that address/command
combination is decoded as a valid access, it will still
complete the transaction as though the parity check was
correct.
The OX16PCI954 does not support any kind of caching or
data buffering in addition to that already provided within the
UARTs by the transmit and receive data FIFOs. In general,
registers in the UARTs and on the local bus can not be pre-
fetched because there may be side-effects on read.
6.2
The OX16PCI954 is a dual-function device, where each
logical function has its own configuration space. All
required fields in the standard header are implemented,
plus the Power Management Extended Capability register
set. The format of the configuration space is shown in
Table 4 overleaf.
In general, writes to any registers that are not implemented
are ignored, and all reads from unimplemented registers
return 0.
Configuration space
OX16PCI954
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