ox16pci954 ETC-unknow, ox16pci954 Datasheet - Page 29

• Manufacturer Part Number: ox16pci954
• Description: Integrated Quad Uart Interface
• Manufacturer: ETC-unknow

7
Each of the four UART channels in the OX16PCI954 operates individually as an OX16C950 high-peformance serial port. Each
channel has its own full set of registers, but all share a common clock and FIFOSEL pin. After a device reset, a common
configuration state is loaded into all four channels, but after this time each can be operated individually through its own 8-byte
block of addressable space.
7.1
Each channel is backward compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the ports
depends on a number of mode settings, which are referred to throughout this section. The modes, conditions and corresponding
FIFO depth are tabulated below:
Note 1: 950 mode configuration is identical to 650 configuration
7.1.1
After a hardware reset, bit 0 of the FIFO Control Register
(‘FCR’) is cleared, hence the UARTs are compatible with
the 16C450. The transmitter and receiver FIFOs (referred
to as the ‘Transmit Holding Register’ and ‘Receiver Holding
Register’ respectively) have a depth of one. This is referred
to as ‘Byte mode’. When FCR[0] is cleared, all other mode
selection parameters are ignored.
7.1.2
Connect FIFOSEL to GND. After a hardware reset, writing
a 1 to FCR[0] will increase the FIFO size to 16, providing
compatibility with 16C550 devices.
7.1.3
Connect FIFOSEL to VDD. Writing a 1 to FCR[0] will now
increase the FIFO size to 128, thus providing a 550 device
with 128 deep FIFOs.
7.1.4
For compatibility with 16C750, connect FIFOSEL to GND.
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a
similar fashion to 16C750, the FIFO size can be further
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
I
NTERNAL
Operation – mode selection
450 Mode
550 Mode
Extended 550 Mode
750 Mode
Extended 550
UART Mode
950
450
550
650
750
OX16C950 UART
1
FIFO
size
128
128
128
128
16
1
FCR[0]
S
0
1
1
1
1
1
Table 13: UART Mode Configuration
Enhanced mode
(EFR[4]=1)
X
0
0
1
0
1
increased to 128 by writing a 1 to FCR[5]. Note that access
to FCR[5] is protected by LCR[7]. i.e., to set FCR[5],
software should first set LCR[7] to temporarily remove the
guard. Once FCR[5] is set, the software should clear
LCR[7] for normal operation.
The 16C750 additional features are available as long as
the UART is not put into Enhanced mode; i.e. ensure
EFR[4] = ‘0’. These features are:
7.1.5
The OX16C950 is compatible with the 16C650 when
EFR[4] is set, i.e. the device is in Enhanced mode. As 650
software drivers usually put the device in Enhanced mode,
running 650 drivers on the one of the UART channels will
result in 650 compatibility with 128 deep FIFOs, as long as
FCR[0] is set. This is regardless of the state of the
FIFOSEL pin. Note that the 650 emulation mode of the
OX16PCI954 provides 128-deep FIFOs rather than the 32
provided by a legacy 16C654.
(guarded with LCR[7] = 1)
Deeper FIFOs
Automatic RTS/CTS out-of-band flow control
Sleep mode
650 Mode
FCR[5]
X
X
X
X
0
1
FIFOSEL
pin
X
X
X
0
1
0
OX16PCI954
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