gal20lv8 Lattice Semiconductor Corp., gal20lv8 Datasheet
gal20lv8
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gal20lv8 Summary of contents
Page 1
... Output Logic Macrocell (OLMC configured by the user. An important subset of the many architecture configura- tions possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility ...
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... GAL20LV8D Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) 3 Part Number Description GAL20LV8D Device Name Speed (ns Low Power Power Ordering # GAL20LV8D-3LJ 70 70 GAL20LV8D-5LJ 70 GAL20LV8D-7LJ _ XXXXXXXX Specifications GAL20LV8 Package 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC ...
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... The following is a list of the PAL architectures that the GAL20LV8D can emulate. It also shows the OLMC mode under which the devices emulate the PAL architecture. ...
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... XOR OE XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL20LV8 Dedicated input or output functions can be implemented as sub- sets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. ...
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... ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 .... MSB LSB PLCC Package Pinout 2640 2703 .... 2630, 2631 .... Byte1 Byte0 5 Specifications GAL20LV8 27 OLMC 26 XOR-2560 AC1-2632 OLMC 25 XOR-2561 AC1-2633 OLMC 24 XOR-2562 AC1-2634 OLMC 23 XOR-2563 AC1-2635 OLMC 21 XOR-2564 ...
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... De- XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL20LV8 signs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control ...
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... ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 .... MSB Specifications GAL20LV8 PLCC Package Pinout 2640 2703 .... 2630, 2631 .... Byte1 Byte0 LSB 7 27 OLMC 26 XOR-2560 ...
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... XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL20LV8 Pins 2 and 16 are always available as data inputs into the AND array. The "center" two macrocells (pins 21 & 23) cannot be used in the input configuration. ...
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... ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 .... MSB Specifications GAL20LV8 PLCC Package Pinout 2640 2703 .... 2630, 2631 .... Byte1 Byte0 LSB 9 27 OLMC XOR-2560 ...
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... MAX. Vin = -100 A Vin = 3. 0. OUT = 3.0V Unused Inputs 1MHz Outputs Open = Specifications GAL20LV8 ) ............................... MIN. TYP. Vss – 0.3 — 2.0 — 2.0 — Vcc+0.5 — — — — — — — ...
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... Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O Specifications GAL20LV8 Over Recommended Operating Conditions TYPICAL UNITS COM COM COM - MIN ...
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... Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL20LV8 INPUT or I/O FEEDBACK CLK VALID INPUT REGISTERED t pd OUTPUT REGISTERED OUTPUT t wl CLK REGISTERED FEEDBACK 12 VALID INPUT ...
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... Output Load Conditions (see figure) GND to 3.0V Test Condition 1.5ns 10% – 90% A 1.5V B 1.5V C See Figure TEST POINT 35pF Specifications GAL20LV8 CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su High Z to Active High at 1.9V 50 High Z to Active Low at 1.0V 50 Active High to High ...
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... NOTE: The electronic signature is included in checksum calcula- tions. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL20LV8D devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device ...
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... Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL20LV8D provides a reset signal to all reg- isters during power-up. All internal registers will have their Q outputs t set low after a specified time ( pr MAX result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins ...
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... RISE -0.4 FALL -0 Delta Tco vs Output Loading Loading 16 RISE 12 FALL 100 150 200 250 300 Output Loading (pF) 16 Specifications GAL20LV8 Normalized Tsu vs Vcc 1.2 RISE 1.1 FALL 1 0.9 0.8 3.60 3.00 3.15 3.30 Supply Voltage (V) Normalized Tsu vs Temp 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 100 125 -55 - Temperature (deg. C) ...
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... Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Voh vs Ioh 3 2.5 2 1.5 1 0.5 0 0.00 5.00 10.00 15.00 20.00 25.00 30.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 3.60 -55 - Temperature (deg. C) Input Clamp (Vik -2.00 -1.50 -1.00 -0.50 Vik (V) 17 Specifications GAL20LV8 Voh vs Ioh 3 2.95 2.9 2.85 2.8 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. 1.40 1.30 1.20 1.10 1.00 0.90 0.80 100 125 Frequency (MHz) 0.00 3.00 4.00 75 100 ...