gal26clv12 Lattice Semiconductor Corp., gal26clv12 Datasheet - Page 11

• Manufacturer Part Number: gal26clv12
• Description: Low Voltage E2 Cmos Pld Generic Array Logic? Gal
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the GAL26CLV12D provides a reset signal to all
registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1 s MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
Typ. Vref = Vcc
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Active Pull-up Circuit
Typical Input
INTERNAL REGISTER
OUTPUT REGISTER
OUTPUT REGISTER
Vref
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
C L K
V c c
Vcc
Vcc
Vcc (min.)
11
t
pr
chronous nature of system power-up, some conditions must be
met to provide a valid power-up reset of the GAL26CLV12D. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Typ. Vref = Vcc
Specifications GAL26CLV12
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
t
wl
t
su
Feedback
Tri-State
Control
Typical Output
Vcc
Active Pull-up Circuit
Feedback
(To Input Buffer)
Vref
PIN
PIN