gal26clv12 Lattice Semiconductor Corp., gal26clv12 Datasheet - Page 9

• Manufacturer Part Number: gal26clv12
• Description: Low Voltage E2 Cmos Pld Generic Array Logic? Gal
• Manufacturer: Lattice Semiconductor Corp.

Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Output Load Conditions (see figure)
Note: fmax with external feedback is calculated from measured
tsu and tco.
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
High Z to Active High at 1.9V
High Z to Active Low at 1.0V
Active High to High Z at 1.9V
Active Low to High Z at 1.0V
f
max with External Feedback 1/(
LOGIC
ARRAY
LOGIC
ARRAY
t
f
su +
max with No Feedback
t
su
t
h
REGISTER
REGISTER
CLK
CLK
1.5ns 10% – 90%
50
50
50
50
50
t
t
GND to 3.0V
co
R
See Figure
su+
1
1.5V
1.5V
t
co)
35pF
35pF
35pF
35pF
35pF
C
L
9
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
*C
FROM OUTPUT (O/Q)
UNDER TEST
L
Specifications GAL26CLV12
includes test fixture and probe capacitance.
f
max with Internal Feedback 1/(
LOGIC
ARRAY
TEST POINT
t
cf
Z
t
pd
0
REGISTER
= 50 , C
CLK
L
= 35pF*
t
su+
t
cf)
+1.45V
R
1