hn58x25512ti Renesas Electronics Corporation., hn58x25512ti Datasheet - Page 17

• Manufacturer Part Number: hn58x25512ti
• Description: Serial Peripheral Interface 512k Eeprom 64-kword ?? 8-bit Electrically Erasable And Programmable Read Only Memory
• Manufacturer: Renesas Electronics Corporation.

HN58X25512I
Data Protect
The protection features of the device are summarized in the following tables. When the Status Register Write Disable
(SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
whether write protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered,
depending on the state of write protect (W):
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull write protect (W) high.
If write protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Write Protected Block Size
0
0
1
1
Protection Modes
1
0
1
0
Note:
Rev.1.00, Dec.18.2006, page 17 of 20
W signal
 If write protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable
 If write protect (W) is driven low, it is not possible to write to the Status Register even if the Write Enable Latch
 By setting the Status Register Write Disable (SRWD) bit after driving write protect (W) low.
 By driving write protect (W) low after setting the Status Register Write Disable (SRWD) bit.
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.
(WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status
Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory
area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also
hardware protected against data modification.
1. As defined by the values in the Block Protected (BP1, BP0) bits of the Status Register, as shown in the Write
BP1
Status register bits
Protected Block Size table.
0
0
1
1
SRWD bit
0
1
0
1
BP0
Software
protected (SPM)
Hardware
protected (HPM)
Mode
None
Upper quarter
Upper half
Whole memory
Status register is writable
(if the WREN instruction
has set the WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Status register is
hardware write
protected. The values in
the BP1 and BP0 bits
cannot be changed.
Write protection of the
Protected blocks
status register
Write protected
Write protected
Protected area*
None
C000h − FFFFh
8000h − FFFFh
0000h − FFFFh
Array addresses protected
Memory protect
1
HN58X25512I
Ready to accept Write
instructions
Ready to accept Write
instructions
Unprotected area*
1