as7c331mntd18a Alliance Memory, Inc, as7c331mntd18a Datasheet - Page 4

• Manufacturer Part Number: as7c331mntd18a
• Description: 3.3v 1m X 18 Pipelined Sram With Ntd
• Manufacturer: Alliance Memory, Inc

Functional Description
The AS7C331MNTD18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory
(SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE LATE Write.
This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or read-modify-write operations.
NTD
one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read
pipeline to clear. With NTD
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for
write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected
by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write operations
to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C331MNTD18A operates with a 3.3V ± 5% power supply for the device core (V
power supply (V
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
12/24/04, v 2.7
™
Parameter
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or
Description
DDQ
1
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package.
1
Symbol
™
C
C
, write and read operations can be used in any order without producing dead bus cycles.
I/O
IN
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
*
*
Test conditions
V
V
OUT
Conditions
IN
= 0V
= 0V
Alliance Semiconductor
Min
®
-
-
1–layer
4–layer
Max
5
7
™
) architecture, featuring an enhanced
Symbol
θ
θ
θ
Unit
JA
JA
JC
DD
pF
pF
AS7C331MNTD18A
). DQ circuits use a separate
Typical
40
22
8
P. 4 of 18
Units
°C/W
°C/W
°C/W