LMH7322SQ National Semiconductor Corporation, LMH7322SQ Datasheet - Page 18

• Manufacturer Part Number: LMH7322SQ
• Description: The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual
• Manufacturer: National Semiconductor Corporation

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In most circumstances this is not an option because the slew
rate of the input signal will vary.
Using Hysteresis
A good way to avoid oscillations and noise during slow slopes
is the use of hysteresis. For this purpose the switching level
is forced to a new level at the moment the input signal crosses
this level. This can be seen in Figure 16.
In this picture there are two dotted lines A and B, both indi-
cating the resulting level at which the comparator output will
switch over. Assume that for this situation the input signal is
connected to the negative input and the switching level
(V
pin, so a resistor connected to this pin determines the varia-
tion of the V
The hysteresis pin must be connected to the V
varied from a short to an open pin. A short to V
highest hysteresis voltage variation and an open pin means
no level variation. The input level of Figure 16 starts much
lower as the reference level and this means that the state of
the input stage is well defined with the inverting input much
lower than the non-inverting input. As a result the output will
be in the high state. Internally the switching level is at A, with
the input signal sloping up, this situation remains until V
REF
) to the positive input. The LMH7322 has a hysteresis
FIGURE 15. Oscillations on Output Signal
REF
level dependent on the state of the output.
FIGURE 16. Hysteresis
EE
EE
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and can be
means the
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IN
18
crosses level A at t=1. Now the output toggles, and the inter-
nal switching level is lowered to level B. So before the output
has the possibility to toggle again, the difference between the
inputs is made sufficient to have a stable situation again.
When the input signal comes down from high to low, the sit-
uation is stable until level B is reached at t=0. At this moment
the output will toggle back, and the circuit is back in the start-
ing situation with the inverting input at a much lower level than
the non inverting input. In the situation without hysteresis, the
output will toggle exactly at V
pens at the internally introduced levels A and B, as can be
seen in Figure 16. Varying the levels A and B due to the
change of the hysteresis resistor will also vary the timing of
t=0 and t=1. When designing a circuit be aware of this effect.
Introducing hysteresis will cause some time shift between
output and input (e.g. duty cycle variations), but will eliminate
undesired switching of the output.
The Output
OUTPUT SWING PROPERTIES
The LMH7322 has differential outputs which means that both
outputs have the same swing but in opposite directions (See
Figure 17). Both outputs swing around the common mode
output voltage (V
midpoint between two equal resistors connected to each out-
put. The absolute value of the difference between both volt-
ages is called V
because of their digital nature. They only cross this level dur-
ing a transition. Due to the symmetrical structure of the circuit,
both output voltages cross at V
output changes from ‘0’ to ‘1’ or vise versa.
LOADING THE OUTPUT
Both outputs are activated when current is flowing through a
resistor that is externally connected to V
voltage should be set 2V below the V
sible to terminate each of the outputs directly with 50Ω, and
if needed to connect through a transmission line with the
same impedance (see Figure 18). Due to the low ohmic na-
ture of the output emitter followers and the 50Ω load resistor,
a capacitive load of several pF does not dramatically affect
the speed and shape of the signal. When transmitting the sig-
nal from one output to any input the termination resistor
should match the transmission line. The capacitive load (C
will distort the received signal. When measuring this input with
a probe, a certain amount of capacitance from the probe is
parallel to the termination resistor. The total capacitance can
be as large as 10 pF. In this case there is a pole at:
f = 1/(2*π*C*R)
f = 1e9/ π
f = 318 MHz
OD
FIGURE 17. Output Swing
O
. The outputs cannot be held at the V
). This voltage can be measured at the
REF
O
. With hysteresis this hap-
regardless of whether the
CCO
. This makes it pos-
T
. The termination
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O
level
P
)