LMH7322SQ National Semiconductor Corporation, LMH7322SQ Datasheet - Page 9

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LMH7322SQ

Manufacturer Part Number
LMH7322SQ
Description
The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual
Manufacturer
National Semiconductor Corporation
Datasheet

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Application Information
INTRODUCTION
The LMH7322 is a high speed comparator with RS(P)ECL
(Reduced Swing Positive Emitter Coupled Logic) outputs,
and is compatible with LVDS (Low Voltage Differential Sig-
naling) if V
outputs gives a high level of suppression for common mode
noise. The very fast rise and fall times of the LMH7322 enable
data transmission rates up to several Gigabits per second
(Gbps). The LMH7322 inputs have a common mode voltage
range that extends 200 mV below the negative supply voltage
thus allowing ground sensing in case of single supply. The
rise and fall times of the LMH7322 are about 160 ps, while the
propagation delay time is about 700 ps. The LMH7322 can
operate over the full supply voltage range of 2.7V to 12V,
while using single or dual supply voltages. This is a very use-
full feature because it provides a flexible way to interface
between several high speed logic families. Several setups are
shown in the application information section “INTERFACE
BETWEEN LOGIC FAMILIES”. The outputs are referenced
to the positive V
at 5V (per comparator, load current excluded.) The LMH7322
is available in a 24-Pin LLP package.
INPUT & OUTPUT TOPOLOGY
All input and output pins are protected against excessive volt-
ages by ESD diodes. These diodes are conducting from the
negative supply to the positive supply. As can be seen in
Figure 1, both inputs are connected to these diodes. Further
protection of the inputs is provided by the two resistors of
250Ω, in conjunction with the string of anti-parallel diodes
connected between both bases of the input stage. This com-
bination of resistors and diodes reduces excessive input volt-
ages over the input stage, but is low enough to maintain
switching speed to the output signal.
Protection against excessive supply voltages is provided by
a power clamp between V
When using this part be aware of situations in which the dif-
ferential input voltage level is such that these diodes are
conducting. In this case the input current is raised far above
the normal value stated in the datasheet tables because input
current is flowing through the bypass diode string between
both inputs.
Input and output topology
Specification definitions
Propagation delay and dispersion
Hysteresis and oscillations
Output
Applying transmission lines
PCB layout
CCO
is set to 2.5V. The use of complementary
CCO
supply rail. The supply current is 23 mA
CC
and GND.
9
The output stage of the LMH7322 is build using two emitter
followers, which are referenced to the V
Each of the output transistors is active when a current is flow-
ing through any external output resistor connected to a lower
supply rail. The output structure is actually the same as for
the old fashioned ECL devices. Activating the outputs is done
by connecting the emitters to a termination voltage which lies
2V below the V
50Ω can be used and a transmission line of 50Ω can be driv-
en. Another method is to connect the emitters through a
resistor to the most negative supply by calculating the right
value for the emitter current in accordance with the datasheet
tables. Both methods are useful, but they each have good and
bad aspects.
The output voltages for ‘1’ and ‘0’ have a difference of ap-
proximately 400 mV and are respectively 1.1V (for the ‘1’) and
1.4V (for the ‘0’) below the V
enough to drive any LVDS input but can also be used to drive
any ECL or PECL input, when the right supply voltage is cho-
sen, especially the right level for the V
FIGURE 2. Equivalent Output Circuitry
FIGURE 1. Equivalent Input Circuitry
CCO
. In this case a termination resistor of
CCO
. This swing of 400 mV is
CCO
CCO
.
(see Figure 2.)
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